• 제목/요약/키워드: Parity

검색결과 1,098건 처리시간 0.026초

A Weighted Block-by-Block Decoding Algorithm for CPM-QC-LDPC Code Using Neural Network

  • Xu, Zuohong;Zhu, Jiang;Zhang, Zixuan;Cheng, Qian
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제12권8호
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    • pp.3749-3768
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    • 2018
  • As one of the most potential types of low-density parity-check (LDPC) codes, CPM-QC-LDPC code has considerable advantages but there still exist some limitations in practical application, for example, the existing decoding algorithm has a low convergence rate and a high decoding complexity. According to the structural property of this code, we propose a new method based on a CPM-RID decoding algorithm that decodes block-by-block with weights, which are obtained by neural network training. From the simulation results, we can conclude that our proposed method not only improves the bit error rate and frame error rate performance but also increases the convergence rate, when compared with the original CPM-RID decoding algorithm and scaled MSA algorithm.

차세대 고정 및 이동 무선랜의 기술 동향

  • 민승욱;최은영;류득수;이석규
    • 정보와 통신
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    • 제22권9호
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    • pp.175-186
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    • 2005
  • 향후 수년 내에 흠, 오피스 및 핫스팟 영역에서 초고속 멀티미디어의 서비스 수요가 폭발적으로 증가할 것으로 전망됨에 따라 IEEE 802.11에서는 200-500Mbps급의 차세대 초고속 무선랜 표준으로서 IEEE 802.11n의 표준안을 제정하는 작업을 진행하고 있다. 새로운 표준에는 무선통신의 다양한 기술들이 표준으로 채택될 전망이다. 논의되고 있는 기술들로는 물리계층에서의 다중 안테나의 사용, 송신 빔 형성, 듀얼 밴드 그리고 LDPC (Low Density Parity Check) 등의 기술과 MAC (Media Access Control) 계층에서의 집합 전송, 블록 전송, 링크 적응 기법 등의 채택이 논의되고 있다. 기존의 무선랜 시스템에서 널리 사용되어온 IEEE 802.11a/b/g와의 호환성을 보장한다. 또한 차세대 무선랜은 차량용 통신 장치를 위한 고속 이동성을 보장하는 표준인 IEEE 802.11p에 대한 논의도 함께 이루어지고 있다. 본 고에서는 표준회의에서 논의되고 있는 후보 기술들과 차세대 무선랜의 기술동향을 살펴본다.

소프트웨어 RAID 파일 시스템에서 오손 블록 교체시에 효율적인 캐슁 기법 (An efficient caching scheme at replacing a dirty block for softwre RAID filte systems)

  • 김종훈;노삼혁;원유헌
    • 한국통신학회논문지
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    • 제22권7호
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    • pp.1599-1606
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    • 1997
  • The software RAID file system is defined as the system which distributes data redundantly across an aray of disks attached to each workstations connected on a high-speed network. This provides high throughput as well as higher availability. In this paper, we present an efficient caching scheme for the software RAID filte system. The performance of this schmem is compared to two other schemes previously proposed for convnetional file systems and adapted for the software RAID file system. As in hardware RAID systems, small-writes to be the performance bottleneck in softwre RAID filte systems. To tackle this problem, we logically divide the cache into two levels. By keeping old data and parity val7ues in the second-level cache we were able to eliminate much of the extra disk reads and writes necessary for write-back of dirty blocks. Using track driven simulations we show that the proposed scheme improves performance for both the average response time and the average system busy time.

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동적 변화구조의 역전달 신경회로와 로보트의 역 기구학 해구현에의 응용 (A Dynamically Reconfiguring Backpropagation Neural Network and Its Application to the Inverse Kinematic Solution of Robot Manipulators)

  • 오세영;송재명
    • 대한전기학회논문지
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    • 제39권9호
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    • pp.985-996
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    • 1990
  • An inverse kinematic solution of a robot manipulator using multilayer perceptrons is proposed. Neural networks allow the solution of some complex nonlinear equations such as the inverse kinematics of a robot manipulator without the need for its model. However, the back-propagation (BP) learning rule for multilayer perceptrons has the major limitation of being too slow in learning to be practical. In this paper, a new algorithm named Dynamically Reconfiguring BP is proposed to improve its learning speed. It uses a modified version of Kohonen's Self-Organizing Feature Map (SOFM) to partition the input space and for each input point, select a subset of the hidden processing elements or neurons. A subset of the original network results from these selected neuron which learns the desired mapping for this small input region. It is this selective property that accelerates convergence as well as enhances resolution. This network was used to learn the parity function and further, to solve the inverse kinematic problem of a robot manipulator. The results demonstrate faster learning than the BP network.

수직 자기기록 채널에서 연집에러에 따른 LDPC 부호의 성능 (Burst Error Performance of LDPC codes on Perpendicular Magnetic Recording Channel)

  • 김상인;이재진
    • 한국통신학회논문지
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    • 제33권11C호
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    • pp.868-873
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    • 2008
  • 본 논문에서는 수직 자기기록 채널에서 연집에러에 따른 LDPC(low density parity check) 부호의 성능을 분석한다. 수직 자기기록 채널에서 연집에러가 발생하면 수신부에서는 채널상태정보(channel state information)를 통하여 연집에러 부분을 알아낸 후 채널검출기의 연판정(Log Likelihood Ratio) 값을 0으로 초기화하는 방법을 사용한다. 패리티 검사 행렬은 부호율이 0.94인 (4336,4096)와 (8672,8192)를 사용한다. 그리고 채널 검출기는 연산량이 적은 SOVA(soft output Viterbi algorithm)를 사용한다.

디젤엔진 위치서보시스템을 위한 고장 식별 (Fault Isolation for a Diesel Engine Actuator)

  • 박태건;허학범;이기상
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 하계학술대회 논문집 B
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    • pp.417-419
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    • 1998
  • In a large diesel engine actuator position servo system, it is impossible to isolate an actuator fault from a load torque with conventional fault detection isolation (FDI) schemes because they are propagated through a channel. This paper deals with a parity equation based residual generation to isolate them in the system. The actuator fault is modelled by a multiplicative type fault that can be characterized as discrepancies between the nominal and actual plant parameters, whereas the load torque is modelled by an additive disturbance. The transformation implemented in the residual generator should be determined on-line to achieve the isolation. Simulation studies show the practical applicability of the FDI scheme.

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Estimating BP Decoding Performance of Moderate-Length Irregular LDPC Codes with Sphere Bounds

  • 정규혁
    • 한국통신학회논문지
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    • 제35권7C호
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    • pp.594-597
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    • 2010
  • This paper estimates belief-propagation (BP) decoding performance of moderate-length irregular low-density parity-check (LDPC) codes with sphere bounds. We note that for moderate-length($10^3{\leq}N{\leq}4\times10^3$) irregular LDPC codes, BP decoding performance, which is much worse than maximum likelihood (ML) decoding performance, is well matched with one of loose upper bounds, i.e., sphere bounds. We introduce the sphere bounding technique for particular codes, not average bounds. The sphere bounding estimation technique is validated by simulation results. It is also shown that sphere bounds and BP decoding performance of irregular LDPC codes are very close at bit-error-rates (BERs) $P_b$ of practical importance($10^{-5}{\leq}P_b{\leq}10^{-4}$).

철도 통신신호에서의 LDPC에 적용에 관한 연구 (The Study of LDPC for Railroad Signal control system)

  • 박주열;김효상;박태기;김봉택;정기석
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2009년도 춘계학술대회 논문집
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    • pp.442-446
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    • 2009
  • As the railway transportation is getting faster and its operation speed has increased rapidly, its signal control has been complicated. For real time signal processing it is very important to prohibit any critical error from causing the system to malfunction. Today, most of the railroad's controling communications between wayside and train are made in one way. Therefore, by using a forward error correction technique, which receiver can actively correct the signal error, we can increase the performance and the stability of the railroad signaling system. In this paper, we introduce low density parity check(LDPC) that is used by next generation wireless communications and DMB technique. We verified that we can achieve low bit error rate(BER) in high signal to noise ratio(SNR) by using LDPC.

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확장 패리티 공간 기법을 이용한 병렬 전원 장치 고장검출 기법 (Extended Parity Space Techniques for Fault Detection in Parallel Power Supply)

  • 최상의;이연석;박건필;정삼기;나인호
    • 한국콘텐츠학회:학술대회논문집
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    • 한국콘텐츠학회 2016년도 춘계 종합학술대회 논문집
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    • pp.425-426
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    • 2016
  • ICT(Information and Communications Technologies)의 빠른 발전으로 직류 전원의 직접 사용이 증가하고 있다. 그러나 대용량 가변가능 직류 전원 장치가 보편화되지 않았으며 현재 ICT 기기들은 내부 또는 외부에 직류 전원 정류 장치를 내장하고 있다. 앞으로 더욱더 많은 기기들이 교류 전원이 아닌 직류 전원을 사용하게 되므로 가변이 가능한 대용량의 직류 전원 장치가 필요하게 될 것이다. 그러나 가변 가능한 구조의 전원장치는 다수의 전원 장치를 병렬로 연결하여야 하므로 고장에 대한 검출 및 분리가 필요하게 된다. 이러한 고장 검출을 위하여 확장 패리티 공간 기법을 적용하였다.

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The Effect of Block Interleaving in an LDPC-Turbo Concatenated Code

  • Lee, Sang-Hoon;Joo, Eon-Kyeong
    • ETRI Journal
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    • 제28권5호
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    • pp.672-675
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    • 2006
  • The effect of block interleaving in a low density parity check (LDPC)-turbo concatenated code is investigated in this letter. Soft decoding can be used in an LDPC code unlike the conventional Reed-Solomon (RS) code. Thus, an LDPC-turbo concatenated code can show better performance than the conventional RS-turbo concatenated code. Furthermore, the performance of an LDPC-turbo code can be improved by using a block interleaver between the LDPC and turbo code. The average number of iterations in LDPC decoding can also be reduced by a block interleaver.

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