• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5C
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• pp.432-438
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• 2010

In this paper we study the effect of bit-to-symbol mappings on the convergence behavior of turbo equalizers employing low-density parity-check (LDPC) codes over high order modulations. We analyze the effective SNR of the outputs from linear minimum mean-squared error (MMSE) equalizers and the convergence property of LDPC decoding for different symbol mappings. Numerical results show that the bit-reliability (BR) mapping provides better performance than random mapping in LDPC-coded turbo equalizers over high order modulations. We also verify the effect of symbol mappings through the noise threshold and error performance.

• Journal of Families and Better Life
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• v.31 no.5
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• pp.65-77
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• 2013

This study was aimed at (1) investigating expectant mothers' prenatal attachment according to variables (age, gestational weeks, perceived health condition, anticipating the gender of the fetus, marriage duration, and parity), (2) analyzing correlations among their prenatal attachment, spousal support, and parenting efficacy, and (3) examining the role of prenatal attachment as a mediator between spousal support and parenting efficacy. For this purpose, 221 expectant mothers living in Seoul completed a 55-item survey. The collected data were analyzed by t-test, one-way ANOVA, Pearson's correlation coefficients, and regression analyses. The findings of this study were as follows. First, among the variables, gestational weeks, perceived health condition, marriage duration, and parity showed significant differences in the scores for the overall prenatal attachment and subordinate factors. Second, there were positive correlations between the expectant mothers' prenatal attachment and spousal support and between their prenatal attachment and parenting efficacy. Third, the expectant mothers' prenatal attachment proved to mediate between spousal support and parenting efficacy. These findings shed light on the significance of prenatal attachment and spousal support during the pregnancy period; therefore, it is essential to develop education programs for expecting parents to enhance prenatal attachment and spousal support and to conduct follow-up studies to verify the effectiveness of the programs.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.2
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• pp.129-142
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• 2016

In Wyner-Ziv coding, video signals are reconstructed by correcting side information generated by block-based motion estimation/compensation at the decoder. The correction is not always accurate due to the limited number of parity bits and early stopping of low-density parity check accumulate (LDPCA) decoding in distributed video coding, or due to the limited number of measurements in distributed compressive video sensing. The blocking artifacts caused by block-based processing are usually conspicuous in smooth areas and degrade the perceptual quality of the reconstructed video. Conventional deblocking filters try to remove the artifacts by treating both sides of the block boundary equally; however, coding errors generated by block-based processing are not necessarily the same on both sides of the block boundaries. Such a block-wise difference is exploited in this paper to improve deblocking for Wyner-Ziv frameworks by designing a filter where the deblocking strength at each block can be non-identical, depending on the reliability of the reconstructed pixels. Test results show that the proposed filter not only improves subjective quality by reducing the coding artifacts considerably, but also gains rate distortion performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.72-79
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• 2014

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.6
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• pp.325-334
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• 2016

Recently, Open Computing Language (OpenCL) has been proposed to provide a framework that supports heterogeneous computing platforms. By using an OpenCL framework, digital communication systems can support various protocols in a unified computing environment to achieve both high portability and high performance. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes for China Multimedia Mobile Broadcasting (CMMB) on a heterogeneous platform. Each step of LDPC decoding has different parallelization characteristics. In this paper, steps suitable for task-level parallelization are executed on the CPU, and steps suitable for data-level parallelization are processed by the GPU. To improve the performance of the proposed OpenCL kernels for LDPC decoding operations, explicit thread scheduling, loop-unrolling, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance by using heterogeneous multi-core processors on a unified computing framework.

• Asian-Australasian Journal of Animal Sciences
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• v.5 no.2
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• pp.375-382
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• 1992

The effect of certain factors such as sex of calf, status of buffalo, season of calving, parity and sire on lactation length and total lactation yield was studied in 391 Nili-Ravi buffaloes. The average lactation length was $301.73{\pm}1.87$ (mean $\pm$ SE) days with a range of 181 to 505 days whereas the average lactation yield was $2031.08{\pm}19.16kg$ and ranged from 1023 to 6535 kg for 984 lactations. The differences in the means of lactation length and lactation yield due to the sex of calf were significant (p<0.05). The status of buffaloes had a significant (p<0.05) effect on lactation length but its effect on lactation yield was non-significant. The season of calving had no effect on lactation length but it influenced the lactation yield significantly. The milk yield was highest ($2150.81{\pm}43.52kg$) in buffaloes which calved in spring and lowest ($1959.92{\pm}30.83kg$) in autumn. The effect of parity on both traits under study was significant (p<0.01). The maximum and minimum lactation lengths of $309.82{\pm}3.96$ and $284.16{\pm}7.17$ days were observed in the first and sixth lactations, respectively. The milk yield was maximum ($2150.38{\pm}58.79kg$) in the seventh lactation and minimum (1818.31 60.04 kg) in the sixth lactation. The influence of sire was significant on lactation length (p<0.05) and milk yield (p<0.01).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.8
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• pp.1839-1844
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• 2015

The low-density parity-check(LDPC) code has been adopted in many communication standards due to its error correcting performance, and the quasi-cyclic LDPC(QC-LDPC) is widely used because of implementation easiness. In the QC-LDPC decoder, a cyclic-shifter is required to rotate data in various sizes. This kind of cyclic-shifters are called multi-size circular shifter(MSCS), and this paper proposes a low-complexity structure for MSCS. In the conventional serially-placed two barrel-rotators, the unnecessary multiplexers are revealed and removed, leading to low-complexity. The experimental results show that the area is reduced by about 12%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.891-898
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• 2014

The DVC (Distributed Video Coding) provides a theoretical basis for the implementation of light video encoder. Conventionally, lots of studies have been focused on the codec scheme of Stanford University that has a feedback channel to control the bit rate finely. However, the codec scheme can not evaluate the qualities of the frames reconstructed by the received parity bits at the decoder side. This paper presents an efficient method of estimating distortion by correcting the virtual channel noises in side information and then facilitating the measurements of the visual qualities. Through several simulations, it is shown that the proposed method is very efficient in estimating the visual qualities of the reconstructed WZ frames.

• Journal of Broadcast Engineering
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• v.15 no.5
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• pp.665-671
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• 2010

In this paper, a turbo equalizer is proposed for the digital video broadcasting for terrestrial - 2nd generation (DVB-T2) system. The proposed turbo equalizer is consisted with the maximum a posteriori (MAP) and low density parity check (LDPC) decoder. The channel information for the soft-input-soft-output (SISO) MAP equalizer is based on the least square (LS) channel estimator. The performance is analyzed through computer simulations in terms of the iteration number.

• Journal of Communications and Networks
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• v.17 no.4
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• pp.339-345
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• 2015

In this paper, we present an iterative reliability-based modified majority-logic decoding algorithm for two classes of structured low-density parity-check codes. Different from the conventional modified one-step majority-logic decoding algorithms, we design a turbo-like iterative strategy to recover the performance degradation caused by the simply flipping operation. The main computational loads of the presented algorithm include only binary logic and integer operations, resulting in low decoding complexity. Furthermore, by introducing the iterative set, a very small proportion (less than 6%) of variable nodes are involved in the reliability updating process, which can further reduce the computational complexity. Simulation results show that, combined with the factor correction technique and a well-designed non-uniform quantization scheme, the presented algorithm can achieve a significant performance improvement and a fast decoding speed, even with very small quantization levels (3-4 bits resolution). The presented algorithm provides a candidate for trade-offs between performance and complexity.