• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.19-28
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• 2000

The parallel inverter is widely utilized because of its fault-tolerance capability, high-current output at constant voltages and system modularity. The conventional paralled inverter usually employes an active and reactive power control or a frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes novel control scheme for equalization of output power between the parallel connected inverters. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employes a instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Futhermore, the proposed constrol scheme is verified through the simulation in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1468-1480
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• 1999

In database systems, join operations are the most complex and time consuming ones which limit performance of such system. Many parallel join algorithms have been proposed for the systems. However, they did not consider data skew, such as attribute value skew (AVS) and join product skew (JPS). In the skewness environments, performance of framework for a uniform load distribution and an efficient parallel join algorithm using the framework to handle AVS and JPS. In our algorithm, we estimate data distributions of input and output relations of join operations using the sampling methodology and evaluate join cost for the estimated data distributions. Finally, using the histogram equalization method we distribute data among nodes to achieve good load balancing among nodes in the local joining phase. For performance comparison, we present simulation model of our algorithm and other join algorithms and present the result of some simulation experiments. The results indicate that our algorithm outperforms other algorithms in the skewed case.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1211-1222
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• 2018

This study presents a power distribution control scheme for a three-phase interleaved parallel DC/DC converter in a battery energy storage system. To extend battery life and increase the power equalization rate, a control method based on the nth order of the state of charge (SoC) is proposed for the charging and discharging processes. In the discharging process, the battery sets with high SoC deliver more power, whereas those with low SoC deliver less power. Therefore, the SoC between each battery set gradually decreases. However, in the two-stage charging process, the battery sets with high SoC absorb less power, and thus, a power correction algorithm is proposed to prevent the power of each particular battery set from exceeding its rated power. In the simulation performed with MATLAB/Simulink, results show that the proposed scheme can rapidly and effectively control the power distribution of the battery sets in the charging and discharging processes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.659-667
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• 2002

In this dissertation, in the Turbo Code used for error correction coding of the recent digital communication systems, we propose a new S-R interleaver that has the better performance than the existing block interleaver, and the Turbo Decoder that has the parallel concatenated New structure using the MAP algorithm. For real-time voice and video services over the third generation mobile communications, the performance of two proposed methods is analyzed by the reduced decoding delay using the variable decoding method by computer simulation over multipath channels of DS-CDMA system. Also, a Modified NCMA based on conventional NCMA is proposed to improve the channel efficiency in the mobile communication system, and is investigated over the multi-user environment of DS-CDMA system through computer simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.