• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.265-268
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• 2002

Parallel-computation is very interesting topic. This paper describes that we apply it into the Boltzmann machine with the Parallel-Transit-Evaluation Method successfully.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.251-260
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• 2002

The parallel/distributed processing with a lot of the idle hosts on the web has the high coot-performance ratio for large-scale applications. It's processing has to show the solutions for unpredictable status such as heterogeneity of hosts, variability of hosts, autonomy of hosts, the supporting performance continuously, and the number of hosts which are participated in computation and so on. In this paper, we propose the strategy of adaptive tack reallocation based on performance the host job processing, spread out geographically Also, It shows the scheme of dynamic host management with dynamic environment, which is changed by lots of hosts on the web during parallel processing for large-scale applications. This paper implements the PDSWeb (Parallel/Distributed Scheme on Web) system, evaluates and applies It to the generation of rendering image with highly intensive computation. The results are showed that the adaptive task reallocation with the variation of hosts has been increased up to maximum 90% and the improvement in performance according to add/delete of hosts.

• Computers and Concrete
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• v.18 no.5
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• pp.1019-1039
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• 2016

In this paper, a parallel algorithm of nonlinear dynamic analysis of three-dimensional (3D) reinforced concrete (RC) frame structures based on the platform of graphics processing unit (GPU) is proposed. Time integration is performed using Newmark method for nonlinear implicit dynamic analysis and parallelization strategies are presented. Correspondingly, a parallel Preconditioned Conjugate Gradients (PCG) solver on GPU is introduced for repeating solution of the equilibrium equations for each time step. The RC frames were simulated using fiber beam model to capture nonlinear behaviors of concrete and reinforcing bars. The parallel finite element program is developed utilizing Compute Unified Device Architecture (CUDA). The accuracy of the GPU-based parallel program including single precision and double precision was verified in comparison with ABAQUS. The numerical results demonstrated that the proposed algorithm can take full advantage of the parallel architecture of the GPU, and achieve the goal of speeding up the computation compared with CPU.

• International Journal of Naval Architecture and Ocean Engineering
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• v.8 no.5
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• pp.434-441
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• 2016

Numerical simulations of 1D Burgers equation and 2D sloshing problem were carried out to study numerical discrepancy between serial and parallel computations. The numerical domain was decomposed into 2 and 4 subdomains for parallel computations with message passing interface. The numerical solution of Burgers equation disclosed that fully explicit boundary conditions used on subdomains of parallel computation was responsible for the numerical discrepancy of transient solution between serial and parallel computations. Two dimensional sloshing problems in a rectangular domain were solved using OpenFOAM. After a lapse of initial transient time sloshing patterns of water were significantly different in serial and parallel computations although the same numerical conditions were given. Based on the histograms of pressure measured at two points near the wall the statistical characteristics of numerical solution was not affected by the number of subdomains as much as the transient solution was dependent on the number of subdomains.

• Journal of the Korean Society for Railway
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• v.8 no.1
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• pp.1-5
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• 2005

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit has been successfully applied to the inductively coupled passive RFTD system working at a frequency of 13.56㎒ in order to process the detection of logical faults more fast and the system has been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates about 15％ In the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• Journal of Communications and Networks
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• v.16 no.4
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• pp.436-446
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• 2014

The high intensity of research and modeling in fields of mathematics, physics, biology and chemistry requires new computing resources. For the big computational complexity of such tasks computing time is large and costly. The most efficient way to increase efficiency is to adopt parallel principles. Purpose of this paper is to present the issue of parallel computing with emphasis on the analysis of parallel systems, the impact of communication delays on their efficiency and on overall execution time. Paper focuses is on finite algorithms for solving systems of linear equations, namely the matrix manipulation (Gauss elimination method, GEM). Algorithms are designed for architectures with shared memory (open multiprocessing, openMP), distributed-memory (message passing interface, MPI) and for their combination (MPI + openMP). The properties of the algorithms were analytically determined and they were experimentally verified. The conclusions are drawn for theory and practice.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.155-164
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• 2015

This paper describes a design and implementation of CABAC decoder, which would handle HEVC syntax elements in adaptively pipelined-parallel computation manner. Even though CABAC offers the high compression rate, it is limited in decoding performance due to context-based sequential computation, and strong data dependency between context models, as well as decoding procedure bin by bin. In order to enhance the decoding computation of HEVC CABAC, the flag-type syntax elements are adaptively pipelined by precomputing consecutive flag-type ones; and multi-bin syntax elements are decoded by processing bins in parallel up to three. Further, in order to accelerate Binary Arithmetic Decoder by reducing the critical path delay, the update and renormalization of context modeling are precomputed parallel for the cases of LPS as well as MPS, and then the context modeling renewal is selected by the precedent decoding result. It is simulated that the new HEVC CABAC architecture could achieve the max. performance of 1.01 bins/cycle, which is two times faster with respect to the conventional approach. In ASIC design with 65nm library, the CABAC architecture would handle 224 Mbins/sec, which could decode QFHD HEVC video data in real time.

• Journal of Mechanical Science and Technology
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• v.18 no.5
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• pp.814-819
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• 2004

The conceptual design of a rotorcraft system involves many different analysis disciplines. The decomposition of such a system into several subsystems can make analysis and design more efficient in terms of the total computation time. Adaptive parallel decomposition makes the structure of the overall design problem suitable to apply the multidisciplinary design optimization methodologies and it can exploit parallel computing. This study proposes a decomposition method which adaptively determines the number and sequence of analyses in each sub-problem corresponding to the available number of processors in parallel. A rotorcraft design problem is solved and as a result, the adaptive parallel decomposition method shows better performance than other previous methods for the selected design problem.

• Proceedings of the KSR Conference
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• 2004.10a
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• pp.1235-1240
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• 2004

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit had been successfully applied to the inductively coupled passive RFID system working at a frequency of 13.56MHz in order to process the detection of logical faults more fast and the system had been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates in the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• Journal of Information Processing Systems
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• v.12 no.4
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• pp.724-740
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• 2016

The performance issues of screening large database compounds and multiple query compounds in virtual screening highlight a common concern in Chemoinformatics applications. This study investigates these problems by choosing group fusion as a pilot model and presents efficient parallel solutions in parallel platforms, specifically, the multi-core architecture of CPU and many-core architecture of graphical processing unit (GPU). A study of sequential group fusion and a proposed design of parallel CUDA group fusion are presented in this paper. The design involves solving two important stages of group fusion, namely, similarity search and fusion (MAX rule), while addressing embarrassingly parallel and parallel reduction models. The sequential, optimized sequential and parallel OpenMP of group fusion were implemented and evaluated. The outcome of the analysis from these three different design approaches influenced the design of parallel CUDA version in order to optimize and achieve high computation intensity. The proposed parallel CUDA performed better than sequential and parallel OpenMP in terms of both execution time and speedup. The parallel CUDA was 5-10x faster than sequential and parallel OpenMP as both similarity search and fusion MAX stages had been CUDA-optimized.