• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1305-1309
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• 2013

The application of the superconducting fault current limiter (SFCL) in a power distribution system is expected to contribute the voltage-sag suppression of the bus line as well as the fault-current reduction of the fault line. However, the application effects of the SFCL on the voltage sag of the bus line including the fault current are dependent on its application location in a power distribution system. In this paper, we investigated the fault current limiting and the voltage sag suppressing characteristics of the SFCL due to its application location such as the outgoing point of the feeder, the bus line, the neutral line and the 2nd side of the main transformer in a power distribution system, and analyzed the trace variations of the bus-voltage and fault-feeder current. The simulated power distribution system, which was composed of the universal power source, two transformers with the parallel connection and the impedance load banks connected with the 2nd side of the transformer through the power transmission lines, was constructed and the short-circuit tests for the constructed system were carried out. Through the analysis on the short-circuit tests for the simulated power distribution system with the SFCLs applied into its representative locations, the effects from the SFCL's application on the power distribution system were discussed from the viewpoints of both the suppression of the bus-voltage sag and the reduction of the fault current.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.11
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• pp.6821-6829
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• 2014

The use of semiconductor devices as a component of eco-friendly motor vehicles has increased and their widespread use as high voltage switches is expected. On the other hand, in the case of high-voltage switches, reliability test equipment is not localized. To test high voltage switches, this paper analyzed the relevant test standards for developing power supplies. In particular, for the automotive semiconductor reliability test, the AEC (Automotive Electronic Council) Q101 was analyzed. Based on that, the standard specifications of the power supply were determined. For the main power circuit, the pull bridge converter was adopted and based on the specification, the circuit parameters were determined and verified by simulation. The interface for the parallel and pattern operation was designed. The characteristics of the power supply were tested.

• Journal of Advanced Navigation Technology
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• v.21 no.1
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• pp.107-112
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• 2017

In recent years, electric shock accidents due to electric leakage currents of household appliances such as computers, TVs, refrigerators, and LED lights are continuously occurring in homes and industrial buildings. And it is not easy to check the leakage current of each household appliances connected in parallel at the rear end of the module. In addition, the leakage current flowing through the path of the normal current other than the existing current leakage circuit breakers are installed in the distribution box, only the function to cut off the power when the leakage. Therefore, there are various disasters such as electric shock and fire caused by short circuit of household appliances, and the risk of such leakage current is seriously presented. In this paper, we propose a method to implement a leakage monitoring system that can be monitored at all times using Zigbee communication based on IEEE 80215.4, which has advantages in low power and low cost among short range wireless communication systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• KIEE International Transactions on Power Engineering
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• v.3A no.1
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• pp.17-26
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• 2003

In this paper, the comparative steady-state operating performance analysis algorithms of the stand-alone single-phase self-excited induction generator (SEIG) is presented on the basis of the two nodal admittance approaches using the per-unit frequency in addition to a new state variable de-fined by the per-unit slip frequency. The main significant features of the proposed operating circuit analysis with the per-unit slip frequency as a state variable are that the fast effective solution could be achieved with the simple mathematical computation effort. The operating performance results in the simulation of the single-phase SEIG evaluated by using the per-unit slip frequency state variable are compared with those obtained by using the per-unit frequency state variable. The comparative operating performance results provide the close agreements between two steady-state analysis performance algorithms based on the electro-mechanical equivalent circuit of the single-phase SEIG. In addition to these, the single-phase static VAR compensator; SVC composed of the thyristor controlled reactor; TCR in parallel with the fixed excitation capacitor; FC and the thyristor switched capacitor; TSC is ap-plied to regulate the generated terminal voltage of the single-phase SEIG loaded by a variable inductive passive load. The fixed gain PI controller is employed to adjust the equivalent variable excitation capacitor capacitance of the single-phase SVC.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.1-12
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• 1999

A new algorithm of constructing binary decision diagram(BDD) for design verification of switch-level circuits is proposed in this paper. In the switch-level circuit, functions are characterized by serial and parallel connections of switches and the final logic values may have high-impedance and unstable states in addition to the logic values of 0 and 1. We extend the BDD to represent functions of switch-level circuits as acyclic graphs so called switch-level binary decision diagram (SLBDD). The function representation of the graph is in the worst case, exponential to the number of inputs. Thus, the ordering of decision variables plays a major role in graph sizes. Under the existence of pass-transistors and domino-logic of precharging circuitry, we also propose an input ordering algorithm for the efficiency in graph sizes. We conducted several experiments on various benchmark circuits and the results show that our algorithm is efficient enough to apply to functional simulation, power estimation, and fault-simulation of switch-level design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.49-58
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• 2015

A floating type of memristor emulator which acts like the behavior of $TiO_2$ memristor has been developed. Most of existing memristor emulators are grounded type which is built disregarding the connectivity with other memristor or other devices. The developed memristor emulator is a floating type whose output does not need to be grounded. Therefore, the emulator is able to be connected with other devices and be utilized for the interoperability test with various other circuits. To prove the floating function of the proposed memristor emulator, a Wheatstone bridge is built by connecting 4 memristor emulators in series and parallel. Also this bridge circuit suggest that it is possible to weight calculation of the neural network synapse.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.331-336
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• 2004

This study focuses on the hardware implementation of fast and low-system-complexity multiplier over GF(2$^{m}$ ). From the properties of an irreducible AOP of degree m. the modular reduction in GF(2$^{m}$ ) multiplicative operation can be simplified using cyclic shift operation. And then, GF(2$^{m}$ ) multiplicative operation can be established using the away structure of AND and XOR gates. The proposed multiplier is composed of m(m+1) 2-input AND gates and (m+1)$^2$ 2-input XOR gates. And the minimum critical path delay is Τ$_{A+}$〔lo $g_2$$^{m}$ 〕Τ$_{x}$ proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.n.

• ETRI Journal
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• v.42 no.5
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• pp.781-789
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• 2020

In this study, an E-band low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) has been designed using silicon-germanium 130-nm bipolar complementary metal-oxide-semiconductor technology to suppress unwanted signal gain outside operating frequencies and improve the signal gain and noise figures at operating frequencies. The proposed impedance-controllable filter has series (R_s) and parallel (R_p) resistors instead of a conventional inductor-capacitor (L-C) filter without any resistor in an interstage matching circuit. Using the impedance-controllable filter instead of the conventional L-C filter, the unwanted high signal gains of the designed E-band LNA at frequencies of 54 GHz to 57 GHz are suppressed by 8 dB to 12 dB from 24 dB to 26 dB to 12 dB to 18 dB. The small-signal gain S₂₁ at the operating frequencies of 70 GHz to 95 GHz are only decreased by 1.4 dB to 2.4 dB from 21.6 dB to 25.4 dB to 19.2 dB to 24.0 dB. The fabricated E-band LNA MMIC with the proposed filter has a measured S₂₁ of 16 dB to 21 dB, input matching (S₁₁) of -14 dB to -5 dB, and output matching (S₂₂) of -19 dB to -4 dB at E-band operating frequencies of 70 GHz to 95 GHz.