• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.153-156
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• 2002

In this paper, we have designed a small size lumped/distributed hybrid element directional coupler using parallel coupled-line theory. a hybrid lumped equivalent circuit for a conventional parallel directional coupler is proposed. The equivalent circuit and design formula for the presented lumped element coupler are derived based on the even- and odd-mode properties of a parallel-coupled line. By using the derived design formula, we have extracted design parameters and designed the 3㏈ and 10㏈ small size lumped element directional couplers at the center frequency of 2Ghz. Excellent agreements between design theory and simulation on the designed directional couplers show the validity of this paper.

• 한국소음진동공학회논문집
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• 제15권9호
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• pp.1003-1008
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• 2005

The acoustic absorption of a multiple layer perforated plate system is very good near the resonance frequency region, while it has been regarded as a demerit that its frequency bandwidth is considerably narrow. In order to overcome such a demerit, the parallel perforated plates with different porosities are proposed. The sound absorption of such system composed of a parallel perforated plate is calculated by an equivalent electroatoustic circuit approach and validated by comparing the calculated absorption coefficients with those measured by the two-microphone impedance tube method. The sound absorptive characteristics and performance of parallel perforated plate systems are discussed from a standpoint of frequency bandwidth related with sound absorption.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.571-573
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• 1988

A new ripple analog-to-digital converter(ADC) has been developed. It consists of two parallel ADCs and a switching network. The circuit operates on the input signal in two serial steps. First a coarse conversion is made to determine the most significant bits by the first parallel ADC. The results control a switching network to connect the series resistor segment, the analog signal is contained within, to the second parallel ADC. At second step, a fine conversion is made to determine the least signification bits by the second parallel ADC. The circuit requires 2(2$\frac{N}{2}$) comparators, 2(2$\frac{N}{2}$) resistors, and 2(2$\frac{N}{2}$) switches for N-bit resolution.

• 조명전기설비학회논문지
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• 제17권5호
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• pp.60-67
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• 2003

본 논문에서는 개폐기의 EMC 성능 개선방안을 연구하였다. 개폐기와 제어함은 멀티 제어 케이블로 연결되었다. 또한 각 장치에는 많은 제어 케이블이 설치되었다. 이들 제어 케이블은 전자부품과 직접 연결된다. 그러므로 제어 케이블은 EMC 성능 향상에 중요한 요소이다. EMC 성능 개선방안으로 제어 케이블과 나란히 병렬접지도체 (Parallel Grinding Conductor, PGC) 설치를 제안하였다. 또한 개폐기 내에 설치된 전압 변성기의 2차 케이력은 차폐 케이블을 사용하고, 차폐의 양단을 접지하는 것을 제안하였다. 개선방안 적용 후 개폐기의 EMC성능이 향상되었음을 확인하였다.

• 전기전자학회논문지
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• 제18권2호
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• pp.228-233
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• 2014

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

• Journal of Mechanical Science and Technology
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• 제17권11호
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• pp.1650-1658
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• 2003

This paper deals with a novel shunt circuit, which is capable of suppressing multimode vibration amplitudes by using a pair of piezoceramic patches. In order to describe the characteristic behaviors of a piezoelectric damper connected with a series and a parallel resistor-negative capacitor branch circuit, the stiffness ratio and loss factor with respect to the non-dimensional frequency are considered. The mechanism of the shunt damper is also described by considering a shunt voltage constrained by shunt impedance. To obtain a guideline model of the piezo/beam system with a negative capacitive shunting, the governing equations of motion are derived through the Hamilton's principle and a piezo sensor equation as well as a shunt-damping matrix is developed. The theoretical analysis shows that the piezo/beam system combined with a series and a parallel resistor-negative capacitor branch circuit developed in this study can significantly reduce the multiple-mode vibration amplitudes over the whole structural frequency range.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.1026-1028
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• 2001

In this paper, proposal circuit proposes that load parallel resonant DC-DC Converter consist of L and C resonant tank circuit. Also, the capacitor$(C_1,\;C2)$ connected in switch are a common using by resonance capacitor and ZVS capacitor. The analysis of proposed circuit uses normalized parameter and characteristic estimation which is needed in each step before design is generally described the proposed circuit with the characteristics of average power and average output voltage etc. Alse, we conform a rightfulness theoretical analysis by comparing a theoretical values and experimental values obtained from experiment using MOSFET as switching devices.

• 전자공학회논문지B
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• 제32B권5호
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• pp.730-736
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• 1995

This paper presents the design of a CMOS programmable slew rate operational amplifier based upon a newly proposed concept, that is a switched parallel current subtraction circuit with adaptive biasing technique. By utilizing the newly designed circuit, it was proven that slew rate was linearly controlled and power dissipation was optimized. If the programmable slew rate amplifier is employed into mixed signal system, it can furnish the convenience of timing control and optimized power dissipation. Simulated data showed the slew rate ranging from 5. 83V/$\mu$s to 41.4V/$\mu$s, power dissipation ranging from 1.13mW to 4.1mW, and the other circuit performance parameters were proven to be comparable with those of a conventional operational amplifier.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권4호
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• pp.175-182
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• 2000

The back-light inverter used in the laptop computer is designed in this paper. It has been difficult for electromagnetic transformer to enhance the efficiency and compact profile of the inverter. In this paper, (1) the piezoelectric transformer (PT) is used for reducing the loss; (2) the volumes of core and winding coil are used in electromagnetic transformer, and (3) the half-bridge series parallel resonant circuit is used in the driver of the inverter. The modified PT for this paper and the equivalent circuit are supported by the simulation program. The result of the experiment shows more than 91% improvement in terms of the efficiency.

• 대한전기학회논문지:전력기술부문A
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• 제50권1호
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• pp.38-44
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• 2001

For double-circuit transmission line systems, an accurate digital distance relaying algorithm immune to the reactance effect is proposed. The apparent impedance calculated by the distance relay is influenced by the combined reactance effect of the fault resistance and the load current as well as the mutual coupling effect caused by the zero-sequence current of the adjacent parallel circuit. To compensate the magnitude and phase of the estimated impedance, this algorithm uses phase angle difference between the zero(positive) sequence of the both side of the system seperated by the fault point. The impedance measuring algorithm presented used a current distribution factor to compensate mutual coupling effect instead of the collected zero-sequence current of the adjacent parallel circuit.