• Title/Summary/Keyword: Parallel Process

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Finite Element Analysis of Shape Rolling Process using Destributive Parallel Algorithms on Cray T3E (병렬 컴퓨터를 이용한 형상 압연공정 유한요소 해석의 분산병렬처리에 관한 연구)

  • Gwon, Gi-Chan;Yun, Seong-Gi
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.24 no.5 s.176
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    • pp.1215-1230
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    • 2000
  • Parallel Approaches using Cray T3E which is NIPP (Massively Parallel Processors) machine are presented for the efficient computation of the finite element analysis of 3-D shape rolling processes. D omain decomposition method coupled with parallel linear equation solver is used. Domain decomposition is applied for obtaining element tangent stifffiess matrices and residual vectors. Direct and iterative parallel algorithms are used for solving the linear equations. Direct algorithm is_parallel version of direct banded matrix solver. For iterative algorithms, the well-known preconditioned conjugate gradient solver with Jacobi preconditioner is also employed. Moreover a new effective iterative scheme with block inverse matrix preconditioner, which is named by present authors, is presented and its results are compared with the one using Jacobi preconditioner. PVM and MPI are used for message passing and synchronization between processors. The performance and efficiency of each algorithm is discussed and comparisons are made among different algorithms.

Finite Element Analysis with STEP in Distributive and Collaborative Environment (분산 협업 환경에서의 유한요소 해석에 관한 연구)

  • Cho, Seong-Wook;Kwon, Ki-Eak
    • Korean Journal of Computational Design and Engineering
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    • v.11 no.5
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    • pp.384-392
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    • 2006
  • In this research, the feasibility of distributed finite element analysis system with STEP and CORBA has been investigated. The enabling technologies such as CORBA and Java play key roles in the development of integrated and geographically distributed application software. In addition to the distribution of analysis modules, numerical solution process itself is again divided into parallel processes using multi-frontal method for computational efficiency. In contrast to the specially designed parallel process for specific hardware, CORBA-based parallel process is well suited for heterogeneous platforms over the network. The idea of Web-based distributed analysis system may be applied to the engineering ASP for design and analysis in the product development processes. We believe that the proposed approach for the analysis can be extended to the entire product development process for sharing and utilizing common product data in the distributed engineering environment, thus eventually provide basis for virtual enterprise.

Distributed Parallel Computing Environment for Java (자바를 위한 분산된 병렬 컴퓨팅 환경)

  • 이상윤;김승호
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.41 no.6
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    • pp.23-37
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    • 2004
  • Since java thread is an object which is treated as independent process within one execution space in the multiprocessing environment, we can use it for independent process of parallel processing. Using thread and synchronization mechanism of java enables us to write parallel application program easily. Therefore, a lot of results are exist which is apply the feature of java that support parallel processing to the distributed computing environment. In this paper, we introduce a system of environment that support parallel execution of thread which is included in legacy java program. The system named TORB(Transparent Object Request Broker) enables us parallel execution of legacy java program after simple converting process, since it support the feature of programming transparency. TORB is extended version of distributed programming tool that is published by our research team. And it had only typical distributed processing feature that is execute a specified function at the specified computer.

Performance Study of Satellite Image Processing on Graphics Processors Unit Using CUDA

  • Jeong, In-Kyu;Hong, Min-Gee;Hahn, Kwang-Soo;Choi, Joonsoo;Kim, Choen
    • Korean Journal of Remote Sensing
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    • v.28 no.6
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    • pp.683-691
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    • 2012
  • High resolution satellite images are now widely used for a variety of mapping applications including photogrammetry, GIS data acquisition and visualization. As the spectral and spatial data size of satellite images increases, a greater processing power is needed to process the images. The solution of these problems is parallel systems. Parallel processing techniques have been developed for improving the performance of image processing along with the development of the computational power. However, conventional CPU-based parallel computing is often not good enough for the demand for computational speed to process the images. The GPU is a good candidate to achieve this goal. Recently GPUs are used in the field of highly complex processing including many loop operations such as mathematical transforms, ray tracing. In this study we proposed a technique for parallel processing of high resolution satellite images using GPU. We implemented a spectral radiometric processing algorithm on Landsat-7 ETM+ imagery using CUDA, a parallel computing architecture developed by NVIDIA for GPU. Also performance of the algorithm on GPU and CPU is compared.

Development of Realtime Parallel Data Communication Interface for Remote Control of 6-DOF Industrial Robot (산업용 6관절 로봇의 원격제어를 위한 실시간 병렬데이터통신 인터페이스)

  • Choi, Myoung-Hwan;Lee, Woo-Won
    • Journal of Industrial Technology
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    • v.21 no.A
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    • pp.97-103
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    • 2001
  • This paper presents the development of the I/O Interface for the real time parallel data communication between controller of a six-axis industrial robot(CRS-A460) and an external computer. The proposed I/O Interface consists of the hardware I/O interface and the software that is downloaded to the robot controller and executed by the controller operating system. The constitution of the digital I/O Port for CRS-A460 robot controller and the digital I/O board for IBM-PC are presented as well as the Process Control Program of the robot controller. The developed protocol for the parallel data communication is described. The data communication is tested, and the performance is analysed. In particular, it is shown that the real-time constraint of the robot controller process is satisfied.

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A Study on the Design of Format Converter for Pixel-Parallel Image Processing (픽셀-병렬 영상처리에 있어서 포맷 컨버터 설계에 관한 연구)

  • 김현기;김현호;하기종;최영규;류기환;이천희
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.269-272
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    • 2001
  • In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

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The Evaluation of Machining Accuracy and the Machine Simulation for Parallel Kinematic Machine Tool(PKMT) (병렬기구 공직기계의 머신시뮬레이션 및 가공정밀도 평가)

  • Shin, Hyeuk;Ryou, Han-Sik;Ko, Hae-ju;Jung, Yoon-gyo
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.8 no.4
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    • pp.41-47
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    • 2009
  • This research deals with evaluation of machining accuracy for Parallel Kinematic Machine Tool(PKMT) applied parallel type robot system with high precision and stiffness. For this purpose, machine simulation is carried out to foreknow collision and interference between workpiece and tool. Furthermore, on the basis of machine simulation data, PKMT is manufactured. Machining accuracy such as cylindricity straightness, squareness, parallelism circularity, concentricity pitch error and yaw error, is measured by using coordinate measuring machine. Test piece for evaluation of machining accuracy is designed and manufactured under the standard of ISO 10791-7.

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The Optimal Skeleton Method of an Image (화상의 골격화에 대한 최적화 방법)

  • 신충호;오무송
    • Journal of Korea Multimedia Society
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    • v.6 no.2
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    • pp.224-229
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    • 2003
  • In this paper, an effective skeleton method is proposed in order to obtain an enhanced digital image of skeleton line. The edge-detection method is applied in the preprocessing stage and after that, the modified Parallel method is applied to obtain the improved image of skeleton line. The existing parallel methods are Zhang, Lu and Wang, and Paul methods. Firstly, a parallel process method Is applied, and the proposed method is applied that the original is compared with the four neighbor pixels and four corner pixels of mask. In conclusion, the proposed method shows an improved connectivity and quality of skeleton line.

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David II: A new architecture for parallel rendering processors with effective memory system (David II: 효과적인 메모리 시스템을 가지는 병렬 렌더링 프로세서)

  • Lee, Kil-Whan;Park, Woo-Chan;Kim, Il-San;Han, Tack-Don
    • Proceedings of the Korea Information Processing Society Conference
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    • 2004.05a
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    • pp.1655-1658
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    • 2004
  • Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture, called DAVID II, resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. The experimental results show that DAVID II achieves almost linear speedup at best case even in sixteen rasterizers.

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An XPDL-Based Workflow Control-Structure and Data-Sequence Analyzer

  • Kim, Kwanghoon Pio
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.13 no.3
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    • pp.1702-1721
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    • 2019
  • A workflow process (or business process) management system helps to define, execute, monitor and manage workflow models deployed on a workflow-supported enterprise, and the system is compartmentalized into a modeling subsystem and an enacting subsystem, in general. The modeling subsystem's functionality is to discover and analyze workflow models via a theoretical modeling methodology like ICN, to graphically define them via a graphical representation notation like BPMN, and to systematically deploy those graphically defined models onto the enacting subsystem by transforming into their textual models represented by a standardized workflow process definition language like XPDL. Before deploying those defined workflow models, it is very important to inspect its syntactical correctness as well as its structural properness to minimize the loss of effectiveness and the depreciation of efficiency in managing the corresponding workflow models. In this paper, we are particularly interested in verifying very large-scale and massively parallel workflow models, and so we need a sophisticated analyzer to automatically analyze those specialized and complex styles of workflow models. One of the sophisticated analyzers devised in this paper is able to analyze not only the structural complexity but also the data-sequence complexity, especially. The structural complexity is based upon combinational usages of those control-structure constructs such as subprocesses, exclusive-OR, parallel-AND and iterative-LOOP primitives with preserving matched pairing and proper nesting properties, whereas the data-sequence complexity is based upon combinational usages of those relevant data repositories such as data definition sequences and data use sequences. Through the devised and implemented analyzer in this paper, we are able eventually to achieve the systematic verifications of the syntactical correctness as well as the effective validation of the structural properness on those complicate and large-scale styles of workflow models. As an experimental study, we apply the implemented analyzer to an exemplary large-scale and massively parallel workflow process model, the Large Bank Transaction Workflow Process Model, and show the structural complexity analysis results via a series of operational screens captured from the implemented analyzer.