• International Journal of Fuzzy Logic and Intelligent Systems
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• 제3권2호
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• pp.187-193
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• 2003

In this paper, a systematic design method of the intelligent PAM fuzzy controller for nonlinear systems using the efficient tools-Linear Matrix Inequality and the intelligent digital redesign is proposed. In order to digitally control the nonlinear systems, the TS fuzzy model is used for fuzzy modeling of the given nonlinear system. The convex representation technique also can be utilized for obtaining TS fuzzy models. First, the analog fuzzy-model-based controller is designed such that the closed-loop system is globally asymptotically stable in the sense of Lyapunov stability criterion. The simulation results strongly convince us that the proposed method has great potential in the application to the industry.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제7권1호
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• pp.77-84
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• 2007

In this paper, Takagi-Sugeno (TS) fuzzy integral control is investigated to regulate the output voltage of an asymmetric half-bridge (AHB) DC/DC converter; First, we model the dynamic characteristics of the AHB DC/DC converter with state-space averaging method and small perturbation at an operating point. After introducing an additional integral state of the output regulation error, we obtain the $5^{th}$-order TS fuzzy model of the AHB DC/DC converter. Second, the concept of the parallel distributed compensation is applied to design the fuzzy integral controller, in which the state feedback gains are obtained by solving the linear matrix inequalities (LMIs). Finally, simulation results are presented to show the performance of the considered design method as the output voltage regulator and compared to the results for which the conventional loop gain method is used.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 G
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• pp.2296-2298
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• 1998

In this paper, an on-chip learning pulse-mode digital neural network with a massively parallel yet compact and flexible network architecture is suggested. Algebraic neural operations are replaced by stochastic processes using pseudo-random sequences and simple logic gates are used as basic computing elements. Using Back-propagation algorithm both feed-forward and learning phases are efficiently implemented with simple logical gates. RNG architecture using LFSR and barrel shifter are adopted to avoid some correlation between pulse trains. Suggested network is designed in digital circuit and its performance is verified by computer simulation.

• 한국지능시스템학회논문지
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• 제12권3호
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• pp.246-254
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• 2002

In this paper auto-tuning scheme of PID controller based on the reference model has been studied for a Process control system by immune algorithm. Up to this time, many sophisticated tuning algorithms have been tried in order to improve the PID controller performance under such difficult conditions. Also, a number of approaches have been proposed to implement mixed control structures that combine a PID controller with fuzzy logic. However, in the actual plant, they are manually tuned through a trial and error procedure, and the derivative action is switched off. Therefore, it is difficult to tune. Since the immune system possesses a self organizing and distributed memory, it is thus adaptive to its external environment and allows a PDP (Parallel Distributed Processing) network to complete patterns against the environmental situation. Simulation results reveal that reference model basd tuning by immune network suggested in this paper is an effective approach to search for optimal or near optimal process control.

• 전기전자학회논문지
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• 제8권2호
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• pp.172-180
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• 2004

본 논문에서는 다치 논리회로를 구현하는 방식 중 전압 모드 방식에서 $neuron(\nu)MOS$ Down-literal circuit(DLC)의 다중 문턱전압 성질을 이용하여 유한체 $GF(3^m)$상에서 모든 항의 계수가 존재하는 기약 다항식에 대한 승산 알고리즘(AOTP)을 적용한 병렬 입-출력 모듈 구조의 승산기의 회로를 제안하였다. 3치 입력 신호가 인가되는 승산기는 뉴런모스 DLC를 이용하여 모듈화되고, 모듈에서 변환된 3치 입력 신호를 Pass 게이트를 통해서 선택하는 방식으로 승산 및 가산 게이트를 구현하였다. 설계된 승산기의 회로들은 +3V의 단일 공급 전원에서 $0.35{\mu}m$ N-well double-poly four-metal CMOS 공정의 모델 파라미터를 사용하여 모의실험이 수행되었다. 모의실험 결과를 통하여 승산기는 샘플링 레이트가 3MHz, 소비전력은 $4{\mu}W$, 출력은 ${\pm}0.1V$이내의 전압레벨을 유지하는 것을 알 수 있다.

• 한국지능시스템학회논문지
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• 제10권2호
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• pp.152-160
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• 2000

본 논문에서는 확장된 병렬 분산 보상기와 최적 극점 배치 방법을 사용한 비선형 시스템의 퍼지 모델 기반 제어기의 분석과 설계 방법을 제안한다. 설계과정을 설명하면 먼저비선형 시스템을 Takagi-Sugeno 퍼지 모델로 표현하고 확장된 병렬 분산 보상기를 사용하여 제어기 규칙을 작성한다. 그리고 최적 극점 배치 방법을 사용하여 국소 상태 궤환 제어기를 설계하고 이를 이용하여 전체의 퍼지논리제어기를 설계한다. 기존의 사용된 병렬 분산 보상기와는 다르게 본 논문에서 새로이 개발된 확장된 병렬 분산 보상기와 최적 극점 배치 방법을 이용함으로써 안정한 국소 퍼지 제어기의 설계뿐만 아니라 추적 제어 목적도 수행할 수 있는 전체의 안정한 퍼지 제어기도 설계할 수 있다. 게다가 전체 퍼지 모델 뿐만 아니라 실제 비선형 시스템에 대해서도 안정도 분석을 행하였다 마지막으로 제안된 퍼지 모델 기반 제어기 설계 방법의 효율성과 가능성을 하나의 시뮬레이션 예를 통하여 증명하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.61.1-61.1
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• 2015

Nanoscale semiconductor plasma processing has become one of the most challenging issues due to the limits of physicochemical fabrication routes with its inherent complexity. The mission of future and emerging plasma processing for development of next generation semiconductor processing is to achieve the ideal nanostructures without abnormal profiles and damages, such as 3D NAND cell array with ultra-high aspect ratio, cylinder capacitors, shallow trench isolation, and 3D logic devices. In spite of significant contributions of research frontiers, these processes are still unveiled due to their inherent complexity of physicochemical behaviors, and gaps in academic research prevent their predictable simulation. To overcome these issues, a Korean plasma consortium began in 2009 with the principal aim to develop a realistic and ultrafast 3D topography simulator of semiconductor plasma processing coupled with zero-D bulk plasma models. In this work, aspects of this computational tool are introduced. The simulator was composed of a multiple 3D level-set based moving algorithm, zero-D bulk plasma module including pulsed plasma processing, a 3D ballistic transport module, and a surface reaction module. The main rate coefficients in bulk and surface reaction models were extracted by molecular simulations or fitting experimental data from several diagnostic tools in an inductively coupled fluorocarbon plasma system. Furthermore, it is well known that realistic ballistic transport is a simulation bottleneck due to the brute-force computation required. In this work, effective parallel computing using graphics processing units was applied to improve the computational performance drastically, so that computer-aided design of these processes is possible due to drastically reduced computational time. Finally, it is demonstrated that 3D feature profile simulations coupled with bulk plasma models can lead to better understanding of abnormal behaviors, such as necking, bowing, etch stops and twisting during high aspect ratio contact hole etch.

• Journal of Communications and Networks
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• 제13권5호
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

• 한국자동차공학회논문집
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• 제13권6호
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• pp.38-47
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• 2005

In this paper, a regenerative braking algorithm is proposed to make the maximum use of the regenerative braking energy for an independent front and rear motor drive parallel HEV. In the regenerative braking algorithm, the regenerative torque is determined by considering the motor capacity, motor efficiency, battery SOC, gear ratio, clutch state, engine speed and vehicle velocity. To implement the regenerative braking algorithm, HEV powertrain models including the internal combustion engine, electric motor, battery, manual transmission and the regenerative braking system are developed using MATLAB, and the regenerative braking performance is investigated by the simulator. Simulation results show that the proposed regenerative braking algorithm contributes to increasing the battery SOC, which recuperates 60 percent of the total braking energy while satisfying the design specification of the control logic. In addition, a control algorithm which limits the regenerative braking is suggested by considering the battery power capacity and dynamic response characteristics of the hydraulic control module.

• 전자공학회논문지A
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• 제33A권10호
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.