• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.20-25
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• 2011

This paper analyzed the application of Superconducting Fault Current Limiter (SFCL) on 22.9 [kV] bus tie in a power distribution system. Commonly, the parallel operations of power main transformers offer a lot of merits. However, when a fault occurs in the parallel operation of power main transformer, the fault currents might exceed the interruption capacity of existing protective devices. To resolve this problem, thus, the SFCL has been studied as the fascinating device. In case that, Particularly, the SFCL could be installed to parallel operation of various power main transformers in power distribution system of the Korea Electric Power Corporation (KEPCO) on 22.9 [kV] bus tie, the effect of the resistance of SFCL could reduce the increased fault currents and meet the interruption capacity of existing protective devices by them. Therefore, we analyzed the effect of application and proposed the proper impedance of the R-type SFCL on 22.9 [kV] bus tie in a power distribution system using PSCAD/EMTDC.

• Genomics & Informatics
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• v.20 no.1
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• pp.14.1-14.4
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• 2022

Permutation testing is a robust and popular approach for significance testing in genomic research that has the advantage of reducing inflated type 1 error rates; however, its computational cost is notorious in genome-wide association studies (GWAS). Here, we developed a supercomputing-aided approach to accelerate the permutation testing for GWAS, based on the message-passing interface (MPI) on parallel computing architecture. Our application, called MPI-GWAS, conducts MPI-based permutation testing using a parallel computing approach with our supercomputing system, Nurion (8,305 compute nodes, and 563,740 central processing units [CPUs]). For 10⁷ permutations of one locus in MPI-GWAS, it was calculated in 600 s using 2,720 CPU cores. For 10⁷ permutations of ~30,000-50,000 loci in over 7,000 subjects, the total elapsed time was ~4 days in the Nurion supercomputer. Thus, MPI-GWAS enables us to feasibly compute the permutation-based GWAS within a reason-able time by harnessing the power of parallel computing resources.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.4
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• pp.388-394
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• 1999

This paper is concerned with an application of Parallel Genetic Algorithms(PGA) to optimal econmic load dispatch(ELD) in power systems. The ELD problem is to minimize the total generation fuel cost of power outputs for all generating units while satisfying load balancing constraints. Genetic Algorithms(GA) is a good candidate for effective parallelization because of their inherent principle of evolving in parallel a population of individuals. Each individual of a population evaluates the fitness function without data exchanges between individuals. In application of the parallel processing to GA, it is possible to use Single Instruction stream, Multiple Data stream(SIMD), a kind of parallel system. The architecture of SIMD system need not data communications between processors assigned. The proposed ELD problem with C code is implemented by SIMSCRIPT language for parallel processing which is a powerfrul, free-from and versatile computer simulation programming language. The proposed algorithms has been tested for 38 units system and has been compared with Sequential Quadratic programming(SQP).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.436-445
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• 2001

In this paper, we introduce modulo ( 2$^n$-1) parallel-processing residue multipliers, using Op Amp circuits, and their technological application to designing binary multipliers. The limit of multiplying speed in computational processing is a serious harrier in the advances of VLSI technology. To solve this problem, we implement a class of modulo ( 2$^n$-1) parallel multipliers having superior time complexity to O( log$_2$( log$_2$( log$_2$$^n$))) by applying Op Amp circuits, while investigating their technological application to binary multipliers. Since they have excellent time & area complexity compared with previous parallel multipliers, and are applicable to designing binary multipliers of the same efficiency, such parallel multipliers possess high academic value. Indexing Terms Modular Multipliers. Binary Multipliers. Parallel Processing, Operational Amplifiers, Mersenne Numbers.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.5
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• pp.41-51
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• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

• Journal of Internet Computing and Services
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• v.9 no.5
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• pp.185-193
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• 2008

An MTBF(mean time between failures) of large scale parallel systems is known to be only an order of several hours, and large computations sometimes result in a waste of huge amount of CPU time, However. the MPI(Message Passing Interface), a de facto standard for message passing parallel programming, suggests no possibility to handle such a problem. In this paper, we propose an application-level fault tolerant computation system, purely on the basis of the current MPI standard without using any non-standard fault tolerant MPI library, that can be used for general scientific synchronous parallel computation.

• Journal of electromagnetic engineering and science
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• v.12 no.2
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• pp.171-175
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• 2012

In this work, a new microstrip-to-substrate integrated waveguide (SIW) transition using the parallel half-mode substrate integrated waveguide (HMSIW) is proposed. The proposed transition consists of three sections : a microstrip, parallel HMSIWs, and an SIW. By inserting the parallel HMSIWs section between the microstrip section and the SIW section, the proposed transition can improve the return loss characteristics of the near cut-off frequency because the HMSIWs section has a lower cut-off frequency than the SIW section (8.6 GHz). The lower cut-off frequency is achieved through gradual electromagnetic field mode changes for a low reflection. The measured return loss is less than 20 dB in the of 9.1~16.28 GHz freqeuncy range for the back-to-back transition. The measured insertion loss is within 1.6 dB for the back-to-back transition. The proposed transition is expected to play an important role in wideband SIW circuits fed by a microstrip.

• Journal of the Korea Society for Simulation
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• v.7 no.1
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• pp.69-83
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• 1998

In this paper, we present the results of simulation by running parallel VHDL simulation on typical MPP(Massively Parallel Processor) systems such as IBM SP2 and SGI Origin 2000. Parallel simulation uses the synchronous protocol and parallel program is implemented using MPI(Message Passing Interface) based on message passing model, so that it can urn on any parallel programming environment which supports MPI, a standard communication library. And then GVT(Global Virtual Time) computation for parallel simulation is based on the global broadcasting with MPI＿Bcast(), which is a standard function in MPI and piggybacking. Our benchmark exhibits that as size of VHDL grows, the parallel simulation has a better performance compared with the sequential simulation. In addition, we also show the results of comparison between IBM SP2 and SGI Origin 2000 by applying the same application to those indirectly.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1655-1658
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• 2003

The application area of parallel mechanism is limited in spite of many advantages of that because the workspace of platform is a very small. Thus enlargement of workspace is important issue in design of parallel mechanism. In this paper a parallel mechanism design method is described using commercial simulation program. Firstly strokes of the assembled parallel mechanism's active joints are simulated from kinetic simulation mode to get required workspace, Secondly, dynamic parameters(velocity, acceleration, force, moment) are simulated for the gravity, friction and exit load. Finally, workspace of moving platform is displayed and workspace of area is simulated by motion analysis. The results of this paper will help engineer to design parallel mechanism with optimize workspace.

• Journal of the Korean Mathematical Society
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• v.49 no.4
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• pp.805-827
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• 2012

In this paper, we first study convergence of a special type of multisplitting methods with preweighting, and then we provide some comparison results of those multisplitting methods. Next, we propose both parallel implementation of an SOR-like multisplitting method with preweighting and an application of the SOR-like multisplitting method with preweighting to a parallel preconditioner of Krylov subspace method. Lastly, we provide parallel performance results of both the SOR-like multisplitting method with preweighting and Krylov subspace method with the parallel preconditioner to evaluate parallel efficiency of the proposed methods.