• Journal of Korea Multimedia Society
• /
• v.25 no.8
• /
• pp.1085-1096
• /
• 2022

The manufacturing industry is continuously pursuing advanced technology and smartization as it converges with innovative technology. Improvement of manufacturing productivity is achieved by monitoring, analyzing, and controlling the facilities and processes of the manufacturing site in real time through a network. In this paper, we proposed a new OPC-UA based digital twin model for smart factory facilities. A testbed system for USB flash drive packaging facility was implemented based on the proposed digital twin model and OPC-UA data communication scheme. Through OPC-UA based digital twin model, equipment and process status information is transmitted and received from PLC to monitoring and control 3D digital models and physical models in real time. The usefulness of the developed digital twin testbed system was evaluated through usability test.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2004.09a
• /
• pp.233-241
• /
• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2004.09a
• /
• pp.211-219
• /
• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Journal of the Microelectronics and Packaging Society
• /
• v.23 no.2
• /
• pp.37-42
• /
• 2016

While datacenter operation cost increases with electricity price rise, many researchers study low-power processor based supercomputers to reduce power consumption of datacenters. Reliability of low-power processors for supercomputers can be of concern since the reliability of many low-power processors are assessed based on mobile use conditions. This paper assessed the reliability of low-power processor packages based on supercomputer use conditions. Temperature cycling was determined as a critical failure cause of low-power processor packages through literature surveys and failure mode, effect and criticality analysis. The package temperature was measured at multiple processor load conditions to examine the relationship between processor load and package temperature. A physics-of-failure reliability model associated with temperature cycling predicted the expected lifetime of low-power processors to be less than 3 years. Recommendations to improve the lifetime of low-power processors were presented based on the experimental results.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.2
• /
• pp.81-86
• /
• 2023

Recently, there has been an increased demand for light-emitting diode (LED) due to the growing emphasis on environmental protection. However, the use of GaN-based sapphire in LED manufacturing leads to the generation of defects, such as dislocations caused by lattice mismatch, which ultimately reduces the luminous efficiency of LEDs. Moreover, most inspections for LED semiconductors focus on evaluating the luminous efficiency after packaging. To address these challenges, this paper aims to detect defects at the wafer stage, which could potentially improve the manufacturing process and reduce costs. To achieve this, image processing and deep learning-based defect detection techniques for Sapphire Epi-Wafer used in Green LED manufacturing were developed and compared. Through performance evaluation of each algorithm, it was found that the deep learning approach outperformed the image processing approach in terms of detection accuracy and efficiency.

• Journal of the Microelectronics and Packaging Society
• /
• v.22 no.3
• /
• pp.73-77
• /
• 2015

This paper presents integrated polymeric spectrometer module which offers compact size, easily-fabricated structure and low cost. The proposed spectrometer module includes the nano diffraction grating with non-uniform pitch and planar optical waveguide with concave mirror to be fabricated by UV imprint lithography. To increase the reflection efficiency, we designed the nano diffraction grating with triangular profiles. The polymeric planar spectrometer includes a spectral bandwidth of 700 nm, resolution of 10 nm and precision below 5 nm. This polymeric planar spectrometer is well-suited for sensor system.

• Proceedings of the KWS Conference
• /
• 2002.10a
• /
• pp.439-449
• /
• 2002

This paper reviews our recent research works on the interconnection technologies in electronic packaging and assembly. At the aspect of advanced joining methods, laser-ultrasonic fluxless soldering technology was proposed. The characteristic of this technology is that the oxide film was removed through the vibration excitated by high frequency laser change in the molten solder droplet. Application researches of laser soldering technology on solder bumping of BGA packages were carried out. Furthermore, interfacial reaction between SnPb eutectic solder and Au/Ni/Cu pad during laser reflow was analyzed. At the aspect of soldered joints' reliability, the system for predicting and analyzing SMT solder joint shape and reliability(PSAR) has been designed. Optimization design method of soldered joints' structure was brought forward after the investigation of fatigue failure of RC chip devices and BGA packages under temperature cyclic conditions with FEM analysis and experimental study. At the aspect of solder alloy design, alloy design method based on quantum was proposed. The macroproperties such as melting point, wettability and strength were described by the electron parameters. In this way, a great deal of the experimental investigations was replaced, so as to realize the design and research of any kinds of solder alloys with low cost and high efficiency.

• Journal of the Microelectronics and Packaging Society
• /
• v.10 no.3
• /
• pp.9-17
• /
• 2003

In this paper, thermo-mechanical and rheological properties of NCPs (Non-Conductive Pastes) depending on silica filler contents and diluent contents were investigated. And then, thermal cycling (T/C) reliability of flip chip assembly using selected NCPs was verified. As the silica filler content increased, thermo-mechanical properties of NCPs were changed. The higher the silica filler content was added, glass transition temperature ($T_g$) and storage modulus at room temperature became higher. While, coefficient of thermal expansion (CTE) decreased. On the other hand, rheological properties of NCPs were significantly affected by diluent content. As the diluent content increased, viscosity of NCP decreased and thixotropic index increased. However, the addition of diluent deteriorated thermo-mechanical properties such as modulus, CTE, and $T_g$. Based on these results, three candidates of NCPs with various silica filler and diluent contents were selected as adhesives for reliability test of flip chip assemblies. T/C reliability test was performed by measuring changes of NCP bump connection resistance. Results showed that flip chip assembly using NCP with lower CTE and higher modulus exhibited better T/C reliability behavior because of reduced shear strain in NCP adhesive layer.

• Current Optics and Photonics
• /
• v.1 no.6
• /
• pp.613-617
• /
• 2017

Due to optimal advances such as chromatic performance, durability, low power consumption, high efficiency, long-lifetime, and excellent environmental friendliness, white LEDs (WLEDs) are widely used in vehicle front lighting, backlighting, decorative lighting, street lighting, and even general lighting. In this paper, the remote packaging WLEDs (RP-WLEDs) with bi-layer red-emitting $Sr_2Si_5N_8:Eu^{2+}$ and yellow-emitting YAG:Ce phosphor was proposed and investigated. The simulation results based on the MATLAB software and the commercial software Light Tools indicated that the color rendering index (CRI) of bi-layer phosphor RP-WLEDs had a significant increase. The CRI had a considerable increase from 72 to 94. In conclusion, the results showed that bi-layer red-emitting $Sr_2Si_5N_8:Eu^{2+}$ and yellow-emitting YAG:Ce phosphor could be a prospective approach for manufacturing RP-WLEDs with enhanced optical properties.

• Journal of the Microelectronics and Packaging Society
• /
• v.8 no.3
• /
• pp.1-9
• /
• 2001

This paper proposes an inspection algorithm for micro ball grid array ($\mu$BGA) solder balls. This algorithm is motivated by the difficulty of finding defect balls by human visual inspection due to their small dimensions. Specifically, it is developed herein an automated vision-based inspection algorithm for $\mu$BGA's, which can inspect solder balls not only for so-called two dimensional errors, such as missings, positions and sizes, but also for height errors. The inspection algorithm uses two dimensional images of $\mu$BGA obtained through special blue illumination, and processes them with a rotation-invariant sub algorithm. It can also detect height errors when a two-camera system is available. Simulation results show that the proposed algorithm is more efficient in detecting ball defects compared with the conventional algorithms.