• 마이크로전자및패키징학회지
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• 제18권1호
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.

• 조명전기설비학회논문지
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• 제29권1호
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• pp.1-8
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• 2015

To produce the white light, there are a single chip method using the blue light and phosphor coating, a multi chip method by mixing R, G, B light.. Multi chip method is proper for the smart lighting system by controling color and color temperature. And color rendering of single chip LED is good by even spectral distribution. To apply application technic like smart light system, this paper analyzed the properties of single chip LED and RGB multi chip LED, and implemented the 2 part subject evaluation for single chip LED and RGB multi chip LED. The first part is comparison of properties for single chip LED and RGB multi chip and second part is color appearance evaluation of 8 colors in each lighting environment.

• 한국정밀공학회지
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• 제13권7호
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• pp.59-65
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• 1996

A major problem in automation of turning operations is the difficulty in obtaining a sufficient and reliable chip control. Therefore it becomes desirable to find a method which can detect the chip form. Newly born chips in usual metal cutting radiate infrared rays. When such chips run out of cutting point quickly, the radiated energy from the zone around the tool is low compared with that of the case when long tangled chips are staying around the tool. The difference in chip pattern can be detected from the output of pyrometer. But, strictly speaking, only the output of pyrometer does not identify the chip form because that is the removal of chip. Therefore, in this paper, a method of the identification of chip form using output of pyrometer and fuzzy inference is developed.

• 한국신뢰성학회지:신뢰성응용연구
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• 제5권2호
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• pp.221-239
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• 2005

General chip SMD parts(chip resistance, chip capacitor, chip varistor etc.) are very wide used electronics parts for IT units. But, failure modes are indistinct for these chip parts. In factory and field the failure modes are recognized to accidental failure mode caused by potential defect. In this paper used chip varistor ALT(Accelerate Life Test) test for verify general failure modes in chip SMD parts. Also the results are useful for general chip SMD ALT tests.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.472-475
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• 2004

Microarray-based DNA chips provide an architecture for multi-analyte sensing. In this paper, we report a new approach for DNA chip microarray fabrication. Multifunctional DNA chip microarray was made by immobilizing many kinds of biomaterials on transducers (particles). DNA chip microarray was prepared by randomly distributing a mixture of the particles on a chip pattern containing thousands of m-scale sites. The particles occupied a different sites from site to site. The particles were arranged on the chip pattern by the random fluidic self-assembly (RFSA) method, using a hydrophobic interaction for assembly.

• 한국신뢰성학회:학술대회논문집
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• 한국신뢰성학회 2005년도 학술발표대회 논문집
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• pp.51-67
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• 2005

General chip SMD parts(chip resistance, chip capacitor, chip varistor etc.) are very wide sed electronics parts for IT units. But, failure modes are indistinct for these chip parts. In factory and field the failure modes are recognized to accidental failure mope caused by potential defect. In this paper used chip varistor ALT(Accelerate Life Test) test for verify general failure modes in chip SMD parts. Also the results are useful for general chip SMD ALT tests.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.57-57
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• 2000

The purpose of this paper is show that an chip mounter can be modeled by stochastic petri nets, and that the simulator to verify a fitness of the program to assemble. The chip mounter can be constructed by using the petri net class (CPetriNet) based on the object-oriented programming. By using this simulator, we can get the information about the description of motion of the chip mounter, and moreover, we can evaluate the productivity.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2003년도 추계학술대회 발표 논문집
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• pp.154-159
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• 2003

Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

• 스마트미디어저널
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• 제1권1호
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• pp.27-35
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• 2012

본 논문은 온칩 네트워크 기반 플랫폼을 이용한 멀티미디어 비디오 코덱의 성능 분석에 대해 기술한다. 최근에 멀티미디어 SoC 통신 구조로 등장한 온칩 네트워크(On-Chip Network)는 기존의 SoC 설계에 사용된 온칩 버스(On-Chip Bus) 구조의 문제점을 해결하는 통신 구조로서 데이터 통신의 병렬성 제공으로 인한 고성능, 재사용성, 확장성을 제공하는 통신 구조이다. 온칩 네트워크 기반 MPEG-4, H.264의 성능과 온칩 버스와 성능을 비교 분석하였다. 실험 결과, 온칩 네트워크 기반 MPEG-4, H.264의 성능이 온칩 버스에 비해 33~56%의 성능이 개선되었다.