• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.47-52
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• 2013

Gold wire has long been used as a proven method of connecting a silicon die to a substrate in wide variety of package types, delivering high yield and productivity. However, with the high price of gold, the semiconductor packaging industry has been implementing an alternate wire material. These materials may include silver (Ag) or copper (Cu) alloys as an alternative to save material cost and maintain electrical performance. This paper will analyze and compare the electrical characteristics of several wire types. For the study, typical 0.6 mil, 0.8 mil and 1.0 mil diameter wires were selected from various alloy types (2N gold, Palladium (Pd) coated/doped copper, 88% and 96% silver) as well as respective pure metallic wires for comparison. Each wire model was validated by comparing it to electromagnetic simulation results and measurement data. Measurements from the implemented test boards were done using a vector network analyzer (VNA) and probe station setup. The test board layout consisted of three parts: 1. Analysis of the diameter, length and material characteristic of each wire; 2. Comparison between a microstrip line and the wire to microstrip line transition; and 3. Analysis of the wire's cross-talk. These areas will be discussed in detail along with all the extracted results from each type the wire.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.185.2-185.2
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• 2014

We have studied the atomic and electronic structure of graphene nanoribbons (GNRs) on a hexagonal boron nitride (h-BN) sheet with intercalated atoms using first-principles calculations. The h-BN sheet is an insulator with the band gap about 6 eV and then it may a good candidate as a supporting dielectric substrate for graphene-based nanodevices. Especially, the h-BN sheet has the similar bond structure as graphene with a slightly longer lattice constant. For the computation, we use the Vienna ab initio simulation package (VASP). The generalized gradient approximation (GGA) in the form of the PBE-type parameterization is employed. The ions are described via the projector augmented wave potentials, and the cutoff energy for the plane-wave basis is set to 400 eV. To include weak van der Waals (vdW) interactions, we adopt the Grimme's DFT-D2 vdW correction based on a semi-empirical GGA-type theory. Our calculations reveal that the localized states appear at the zigzag edge of the GNR on the h-BN sheet due to the flat band of the zigzag edge at the Fermi level and the localized states rapidly decay into the bulk. The open-edged graphene with a large corrugation allows some space between graphene and h-BN sheet. Therefore, atoms or molecules can be intercalated between them. We have considered various types of atoms for intercalation. The atoms are initially placed at the edge of the GNR or inserted in between GNR and h-BN sheet to find the effect of intercalated atoms on the atomic and electronic structure of graphene. We find that the impurity atoms at the edge of GNR are more stable than in between GNR and h-BN sheet for all cases considered. The nickel atom has the lowest energy difference of ~0.2 eV, which means that it is relatively easy to intercalate the Ni atom in this structure. Finally, the magnetic properties of intercalated atoms between GNR and h-BN sheet are investigated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.345-345
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• 2008

최근 전자 소자의 고주파화, 소형화에 대한 요구가 증대 되면서 많은 소자들을 하나의 시스템에 3차원적으로 실장시키는 SOP (System-on-Package)가 새로운 대안으로 떠오르고 있으며 SOP를 실현하기 위해서는 집적기판에 대한 저온화 공정 기술이 절실히 필요한 실정이다. 현재 집적기판에 사용되는 재료로서 세라믹이 널리 알려져 있지만 세라믹은 취성이 있으며 $1000^{\circ}C$ 이상의 고온화 공정 프로세스를 필요로 하는 근본적인 약점이 있다. 이에 본 연구에서는 상온에서 고속으로 치밀한 성막을 가능케 하는 Aerosol Deposition Method (ADM)를 이용하여 최초로 세라믹-폴리머 복합체 후막을 성공적으로 제작하였다. XRD와 FT-IR 분석 결과 $Al_2O_3$-PMMA, $Al_2O_3$-PI 혼합물을 출발 파우더로 사용하여 제조한 후막이 세라믹-폴리머 복합체임을 확인할 수 있었다. 또한 SEM 분석결과 $Al_2O_3$-PMMA 복합체와 $Al_2O_3$-PI 복합체의 표면 양상이 매우 다르다는 점을 확인하였으며 $Al_2O_3$-PMMA 복합체의 성막률이 $Al_2O_3$-PI 복합체의 성막률에 비해 매우 낮음을 확인하였다. 이러한 현상들은 폴리머 파우더들의 경도와 탄성 차이 때문인 것으로 사료되어 이를 증명하기 위한 실험을 실시하였다. 결국 PMMA 막과 PI 막에 대한경도측정결과와 PMMA 파우더와 PI 파우더의 유성 볼밀링 전후에 대한 SEM 이미지를 통해 PMMA 파우더가 PI 파우더에 비해 경도가 낮으며 반면 탄성이 높다는 것을 간접적으로 확인할 수 있었다. 이와 같은 분석을 통하여 ADM을 이용한 세라믹-폴리머 복합체 후막의 제조에 있어 폴리머 파우더의 경도와 탄성이 매우 큰 영향을 미친다는 것을 알 수 있었다. 본 연구에서는 세라믹-폴리머 복합체 후막을 성공적으로 제조하기 위해서 폴리머 파우더의 적절한 선택이 중요함을 알 수 있었으며 ADM을 이용한 세라믹-폴리머 복합체 후막의 제조에 대한 가이드 라인을 제시할 수 있을 것으로 기대된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.8
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• pp.614-619
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• 2013

Recently, remote phosphor is reported for white LED enhancing of phosphor efficiency compared with conventional phosphor-based W-LED. In this study, Remote phosphor was produced by screen printing coating on glass substrate with phosphor contents rated paste and heat treatment. The paste consists of phosphor, lowest softening glass frit and organic binders. Remote phosphor can be well controlled by varying the phosphor content rated paste. After mounting remote phosphor on top of blue LED chip, CCT, CRI, and luminance efficiency were measured. The measurement results showed that CCT, CRI, and luminance efficiency were 6,645, 68, and 1,16l m/W in phosphor 80 wt.% remote phosphor sintered at $600^{\circ}C$.

• Journal of the Korean Ceramic Society
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• v.51 no.6
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• pp.533-538
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• 2014

Today, silicon and epoxy resin are used as materials of conversion lenses for white LEDs on the basis of their good bonding and transparency in LED packages. But these materials give rise to long-term performance problems such as reaction with water, yellowing transition, and shrinkage by heat. These problems are major factors underlying performance deterioration of LEDs. In this study, in order to address these problems, we fabricated a conversion lenses using glass, which has good chemical durability and is stable to heat. The fabricated conversion lenses were applied to a remote phosphor type. In this experiment, the conversion lens for white LED was coated on a glass substrate by a screen printing method using paste. The thickness of the coated conversion lens was controlled during 2 or 3 iterations of coating. The conversion lens fabricated under high heat treatment temperature and with a thin coating showed higher luminance efficiency and CCT closer to white light than fabricated lenses under low heat treatment temperature or a thick coating. The conversion lens with $32{\mu}m$ coating thickness showed the best optical properties: the measured values of the CCT, CRI, and luminance efficiency were 4468 K, 68, and 142.22 lm/w in 20 wt% glass frit, 80 wt% phosphor with sintering at $800^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.36-36
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• 2007

본 논문에서는 SoP-L(System on Package-Laminates) 기술을 이용하여 이종의 유전율을 가진 유기물 적층 기반의 수동소자를 이용한 GSM/DCS 대역 분리용 diplexer를 설계, 제작하였고 그 특성을 고찰하였다. SoP-L 기술은 LTCC기술과 같은 타 SoP 기술과 비교해서 이종의 물질을 접합하는데 용이하고 공정비용이 저렴하다. 이러한 장점을 이용하여 캐때시터는 유전율 40의 고유전율 재료를 사이에 두고 구성하였고, 인덕터 부문에는 유전율 4률 적용, 정방혈 스파이럴 구조로 두 개 층으로 구성하여 소형화를 이룰 수 있었다. 제작 시에 구리와 유기물을 적층, patterning 하였고, 수직 via hole 을 형성하고 구리의 무전해, 전해 도금 과정을 거쳐 각 소자를 연결하였다. 이러한 과정을 거쳐 제작된 diplexer의 GSM 저역 통과 필터는 0.52 dB이하의 삽입손실과 20 dB 이상의 반사손실을 가지고 DCS 통과 대역 부근에 notch 가 존재하도록 설계함으로써 DCS 통과 대역에서 17 dB 이상의 저지특성을 나타내었다. DCS 고역 통과 필터는 1.2 dB 이하의 삽입손실과 16 dB 이상의 반사손실을 가지며 GSM 통과 대역 부근에 notch를 가지도록 설계하여 GSM 통과대역에서 32 dB 이상의 저지특성을 나타내었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.369-370
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• 2005

LTCC (Low Temperature Cofired Ceramic) technology is one of technologies which can realize SIP (System-In-a-Package). In this paper realization of gas sensor using LTCC technology was described. In the conventional gas sensor structure, wire bonding method is generally used as an interconnection method whereas in the LTCC sensor structure, via was used for the interconnection. As sensing materials, $SnO_2$ was adopted. The effect of frit glass portion on the adhesion of the sensing material to the LTCC substrate and the electrical conductivity of the sensing material were analyzed. AgPd, PdO, Pt was added to the sensing material as an additive for improving the gas sensitivity and electrical conductivity and the effect of the amount of additives in the sensing material on the electrical conductivity was investigated. The effect of the amount of frit glass in the termination on the sensor performance, especially mechanical integrity, was considered and the crack initiation and propagation in the boundary between the sensing material and the termination was studied.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.381-381
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• 2010

$(ZrO_2)_{0.66}(HfO_2)_{0.34}$ thin films as gate dielectrics have been proposed to overcome the problems of tunneling current and degradation mobility inachieving a thin equivalent oxide thickness. An extremely thin $SiO_2$ layer is used in order to separate the carrier in MOSFET channel from the dielectric field fluctuation caused by phonons in the dielectric which decreases the carrier mobility. The electronic and optical properties influenced the device performance to a great extent. $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ dielectric films on p-Si (100) were grown by atomic layer deposition method, for which the conduction band offsets, valence band offsets and band gapswere obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence and conduction band offset values for $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ dielectric thin film, grown on Si substrate were about 5.34, 2.35 and 1.87 eV respectively. This band alignment was similar to that of $ZrO_2$. In addition, The dielectric function (k, $\omega$), index of refraction n and the extinction coefficient k for the $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ thin films were obtained from a quantitative analysis of REELS data by comparison to detailed dielectric response model calculations using the QUEELS-$\varepsilon$(k, $\omega$)-REELS software package. These optical properties are similar with $ZrO_2$ dielectric thin films.

• Microbiology and Biotechnology Letters
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• v.49 no.1
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• pp.65-74
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• 2021

Serine proteases are the most versatile proteolytic enzymes with tremendous applications in various industrial processes. This study was designed to investigate the biochemical properties, critical residues, and the catalytic potential of alkaline serine protease using in-silico approaches. The primary sequence was analyzed using ProtParam, SignalP, and Phyre2 tools to investigate biochemical properties, signal peptide, and secondary structure, respectively. The three-dimensional structure of the enzyme was modeled using the MODELLER program present in Discovery Studio followed by Molecular Dynamics simulation using GROMACS 5.0.7 package with CHARMM36m force field. The proteolytic potential was measured by performing docking with casein- and keratin-enriched residues, while the effect of the inhibitor was studied using phenylmethylsulfonyl fluoride, (PMSF) applying GOLDv5.2.2. Molecular weight, instability index, aliphatic index, and isoelectric point for serine protease were 39.53 kDa, 27.79, 82.20 and 8.91, respectively. The best model was selected based on the lowest MOLPDF score (1382.82) and DOPE score (-29984.07). The analysis using ProSA-web revealed a Z-score of -9.7, whereas 88.86% of the residues occupied the most favored region in the Ramachandran plot. Ser327, Asp138, Asn261, and Thr326 were found as critical residues involved in ligand binding and execution of biocatalysis. Our findings suggest that bioengineering of these critical residues may enhance the catalytic potential of this enzyme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.1-5
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• 2010

We developed a novel micro-electro mechanical systems (MEMS) test socket using silicon on insulator (SOI) substrate with the cantilever array structure. We designed the round shaped cantilevers with the maximum length of $350{\mu}m$, the maximum width of $200{\mu}m$ and the thickness of $10{\mu}m$ for $650{\mu}m$ pitch for 8 mm x 8 mm area and 121 balls square ball grid array (BGA) packages. The MEMS test socket was fabricated by MEMS technology using metal lift off process and deep reactive ion etching (DRIE) silicon etcher and so on. The MEMS test socket has a simple structure, low production cost, fine pitch, high pin count and rapid prototyping. We verified the performances of the MEMS test sockets such as deflection as a function of the applied force, path resistance between the cantilever and the metal pad and the contact resistance. Fabricated cantilever has 1.3 gf (gram force) at $90{\mu}m$ deflection. Total path resistance was less than $17{\Omega}$. The contact resistance was approximately from 0.7 to $0.75{\Omega}$ for all cantilevers. Therefore the test socket is suitable for BGA integrated circuit (IC) packages tests.