• 전기전자학회논문지
• /
• 제14권3호
• /
• pp.250-255
• /
• 2010

본 논문에서는 DTMOS(Dynamic Threshold voltage MOSFET) 스위칭 소자를 사용한 인터리브 방식의 전원제어 장치(PMIC)를 제안하였다. 휴대기기에 필요한 높은 출력 전압과 낮은 출력 전압을 제공하기 위하여 벅-부스트 컨버터를 사용하였다. 또한, 높은 출력 전류에서 고 전력 효율을 얻기 위하여 PWM(Pulse Width Modulation) 제어 방식을 사용하였다. 낮은 온-저항을 갖는 DTMOS를 사용하여 도통 손실을 감소시켰으며 인터리브 방식을 사용하여 출력 리플을 감소시켰다. 1mA 이하의 대기모드에서도 높은 효율을 구현하기 위하여 LDO를 설계하였다.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2017년도 추계학술대회
• /
• pp.109-110
• /
• 2017

본 논문에서는 듀얼 액티브 브릿지에서 SPWM(Single Pulse Width Modulaton)과 DPWM(Dual Pulse Witdh Modulation)을 적용하였을 때, 인덕터 전류의 특성을 비교하고자 한다. 인덕터 전류의 특성을 이론적으로 분석하고, 실험을 통해서 결과를 분석하였다.

• Journal of Power Electronics
• /
• 제17권3호
• /
• pp.653-663
• /
• 2017

Multilevel active neutral-point-clamped (ANPC) converter combines the advantages of three-level ANPC converter and multilevel flying capacitor (FC) converter. However, multilevel ANPC converter often suffers from capacitor voltage balancing problems. In order to solve the capacitor voltage balancing problems for five-level ANPC converter, phase-shifted pulse width modulation (PS-PWM) is used, which generally provides natural voltage balancing ability. However, the natural voltage balancing ability depends on the load conditions and converter parameters. In order to eliminate voltage deviations under steady-state and dynamic conditions, the active voltage-balancing control (AVBC) methods of floating capacitors and dc-link capacitors based on PS-PWM are proposed. First, the neutral-point current is regulated to balance the neutral-point voltage by injecting zero-sequence voltage. After that, the duty cycles of the redundant switch combinations are adjusted to balance the floating-capacitor voltages by introducing moderating variables for each of the phases. Finally, the effectiveness of the proposed AVBC methods is verified by experimental results.

• 전력전자학회논문지
• /
• 제19권6호
• /
• pp.488-493
• /
• 2014

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

• Journal of Power Electronics
• /
• 제18권2호
• /
• pp.604-614
• /
• 2018

This paper proposes a synchronous switching technique for a Vienna rectifier that uses carrier-based pulse width modulation (CB-PWM). A three-phase Vienna rectifier, similar to a three-level T-type converter with three back-to-back switches, is used as a PWM rectifier. Conventional CB-PWM requires six independent gate signals to operate back-to-back switches. When internal switches are operated synchronously, only three independent gate signals are required, which simplifies the construction of gate driver circuits. However, with this method, total harmonic distortion of the input current is higher than that with conventional CB-PWM switching. A reactive current injection technique is proposed to improve current distortion. The performance of the proposed synchronous switching method and the effectiveness of the reactive current injection technique are verified using simulations and experiments performed with a set of Vienna rectifiers rated at 5 kW.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 하계종합학술대회논문집
• /
• pp.847-850
• /
• 1998

One of the most difficult problem of designing VLSI is a mixed-circuit design, that is to design circuit containing both analog parts and digital parts. Digital to analog converter and analog to digital converter is a typical case. Especially it can be a serious problem when mixed circuit are put into a large digital circuit like microcontroller. However nowadays this problem is settled by separating analog circuit parts outside the IC. This technique is based on converting a digital signal into a pulse sequence. Then an analog signal is obtained by averaging this pulse sequence at the external low-pass filter. An anlog to digital converter is designed using a stochastic logic instead of a traditional PWM (pulse-width modulation) signal and ins implemente dusing FPGa. Stochastic pulse sequence can be made as a simple circuits and moreover can be mathematically processed by simple circuits -AND gates. The spectral property of stochastic pulse sequence method is better than that of PWM method. So it make easy to design a external low-pass filter. This technique has important advantages, especially the reduction of the ADC cost.

• Journal of Power Electronics
• /
• 제14권6호
• /
• pp.1314-1321
• /
• 2014

A new simplified topology for a dynamic voltage restorer (DVR) based on direct converter with a reduced number of switches is presented. The direct converter is fabricated using only three bi-directional controlled switches. The direct converter is connected between the grid and center-tapped series transformer. The center-tapped series transformer is used to inject the compensating voltage synthesized by the direct converter. The DVR can properly compensate for long-duration, balanced, and unbalanced voltage sag and swell by taking power from the grid. The switches are driven by ordinary pulse width modulation signals. Simulation and hardware results validate the idea that the proposed topology can mitigate sag of 50% and swell of unlimited quantity.

• 전자공학회논문지SC
• /
• 제47권1호
• /
• pp.62-66
• /
• 2010

순수한 수동소자들을 사용하여 영전류 영전압에서 소프트하게 스위칭 동작하는 펄스 폭 변조 의사 공진 컨버터를 소개한다. 사용된 수동 소자망은 폴딩 스너버망의 변형된 형태로 컨버터의 주 정류 다이오드의 역 복귀 전류를 제거시켜 주고 스위칭 소자 MOSFET를 소프트하게 스위칭 시킨다. 효율도 능동 스너버형과 비슷한 수준이고 회로 구성이 간단하여 구현하기 쉬우며 중 출력(수 KW이하) 정전압 공급원에 적합하다.

• Journal of Power Electronics
• /
• 제6권3호
• /
• pp.187-194
• /
• 2006

A new asymmetrical pulse width modulation (PWM) half bridge converter with improved ZVS performance is proposed. The ZVS operation of the proposed converter can be maintained from no load to full load conditions since the magnetizing current of the transformer contributes to the ZVS operation at light loads without considerable conduction loss of the transformer and switch. Synchronous rectification is employed to reduce the rectification loss. Operational principles, large signal modeling, ZVS analysis and design equations are presented. Experimental results demonstrate that the proposed converter can achieve a large ZVS range and significant improvement in efficiency for a 100W (5V, 20A) prototype converter.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2011년도 추계학술대회
• /
• pp.398-401
• /
• 2011

본 논문에서는 고효율의 CMOS PWM DC-DC 벅 변환기를 설계하였다. 설계된 CMOS PWM DC-DC 벅 변환기는 입력전압(3.4-3.9V)로부터 일정한 출력전압(1-2.8V)을 생성한다. Inductor-based 방식을 택하였고, 제어 대상은 전류이며, Pulse Width Modulation(PWM) 모드로 동작한다. 회로 구성은 Power Switch, Pulse Width Generation, Buffer, Zero Current Sensing, Current Sensing Circuit, Clock & Ramp generation, V-I Converter, Soft Start, Compensator, Modulator 등 이다. 제안된 CMOS PWM DC-DC 벅 컨버터는 Switching Frequency가 약 1MHz이고, 부하 전류가 약 40mA이상부터 CCM동작을 하며 100mA일 때 98.71%의 최대 효율을 갖는다. 또한, 출력전압 리플은 0.98mV이다(입력전압 3.5V, 출력전압 2.5V 기준). 제안된 회로의 검증을 위해 CMOS $0.18{\mu}m$ 공정을 이용하여 시뮬레이션을 수행하였다.