• Journal of IKEEE
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• 제14권3호
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• pp.250-255
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• 2010

The interleaved power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. The buck-boost converter used to provide the high output voltage and low output voltage for portable applications. Also we used the PWM(Pulse Width Modulation) control method for high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The interleaved PMIC to reduce output ripple. And step-down DC-DC converter in stand-by mode below 1mA is designed with LDO in order to achive high efficiency.

• Proceedings of the KIPE Conference
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• 전력전자학회 2017년도 추계학술대회
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• pp.109-110
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• 2017

본 논문에서는 듀얼 액티브 브릿지에서 SPWM(Single Pulse Width Modulaton)과 DPWM(Dual Pulse Witdh Modulation)을 적용하였을 때, 인덕터 전류의 특성을 비교하고자 한다. 인덕터 전류의 특성을 이론적으로 분석하고, 실험을 통해서 결과를 분석하였다.

• Journal of Power Electronics
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• 제17권3호
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• pp.653-663
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• 2017

Multilevel active neutral-point-clamped (ANPC) converter combines the advantages of three-level ANPC converter and multilevel flying capacitor (FC) converter. However, multilevel ANPC converter often suffers from capacitor voltage balancing problems. In order to solve the capacitor voltage balancing problems for five-level ANPC converter, phase-shifted pulse width modulation (PS-PWM) is used, which generally provides natural voltage balancing ability. However, the natural voltage balancing ability depends on the load conditions and converter parameters. In order to eliminate voltage deviations under steady-state and dynamic conditions, the active voltage-balancing control (AVBC) methods of floating capacitors and dc-link capacitors based on PS-PWM are proposed. First, the neutral-point current is regulated to balance the neutral-point voltage by injecting zero-sequence voltage. After that, the duty cycles of the redundant switch combinations are adjusted to balance the floating-capacitor voltages by introducing moderating variables for each of the phases. Finally, the effectiveness of the proposed AVBC methods is verified by experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• 제19권6호
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• pp.488-493
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• 2014

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

• Journal of Power Electronics
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• 제18권2호
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• pp.604-614
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• 2018

This paper proposes a synchronous switching technique for a Vienna rectifier that uses carrier-based pulse width modulation (CB-PWM). A three-phase Vienna rectifier, similar to a three-level T-type converter with three back-to-back switches, is used as a PWM rectifier. Conventional CB-PWM requires six independent gate signals to operate back-to-back switches. When internal switches are operated synchronously, only three independent gate signals are required, which simplifies the construction of gate driver circuits. However, with this method, total harmonic distortion of the input current is higher than that with conventional CB-PWM switching. A reactive current injection technique is proposed to improve current distortion. The performance of the proposed synchronous switching method and the effectiveness of the reactive current injection technique are verified using simulations and experiments performed with a set of Vienna rectifiers rated at 5 kW.

• Proceedings of the IEEK Conference
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.847-850
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• 1998

One of the most difficult problem of designing VLSI is a mixed-circuit design, that is to design circuit containing both analog parts and digital parts. Digital to analog converter and analog to digital converter is a typical case. Especially it can be a serious problem when mixed circuit are put into a large digital circuit like microcontroller. However nowadays this problem is settled by separating analog circuit parts outside the IC. This technique is based on converting a digital signal into a pulse sequence. Then an analog signal is obtained by averaging this pulse sequence at the external low-pass filter. An anlog to digital converter is designed using a stochastic logic instead of a traditional PWM (pulse-width modulation) signal and ins implemente dusing FPGa. Stochastic pulse sequence can be made as a simple circuits and moreover can be mathematically processed by simple circuits -AND gates. The spectral property of stochastic pulse sequence method is better than that of PWM method. So it make easy to design a external low-pass filter. This technique has important advantages, especially the reduction of the ADC cost.

• Journal of Power Electronics
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• 제14권6호
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• pp.1314-1321
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• 2014

A new simplified topology for a dynamic voltage restorer (DVR) based on direct converter with a reduced number of switches is presented. The direct converter is fabricated using only three bi-directional controlled switches. The direct converter is connected between the grid and center-tapped series transformer. The center-tapped series transformer is used to inject the compensating voltage synthesized by the direct converter. The DVR can properly compensate for long-duration, balanced, and unbalanced voltage sag and swell by taking power from the grid. The switches are driven by ordinary pulse width modulation signals. Simulation and hardware results validate the idea that the proposed topology can mitigate sag of 50% and swell of unlimited quantity.

• Journal of the Institute of Electronics Engineers of Korea SC
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• 제47권1호
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• pp.62-66
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• 2010

A new soft recovery pulse width modulation quasi resonant converter composed only passive devices snubber network is proposed. This passive devices snubber network is revised form of folding snubber network that suppressed the reverse recovery current of main rectify diode in PWM converter. It also makes the MOSFET switching devices operate in soft state. The efficient of the proposed converter is almost same level to that of the converter of active snubber type. The overall circuit is simple and easy to realized. Therefore, it is suitable to apply to middle range output power source.

• Journal of Power Electronics
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• 제6권3호
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• pp.187-194
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• 2006

A new asymmetrical pulse width modulation (PWM) half bridge converter with improved ZVS performance is proposed. The ZVS operation of the proposed converter can be maintained from no load to full load conditions since the magnetizing current of the transformer contributes to the ZVS operation at light loads without considerable conduction loss of the transformer and switch. Synchronous rectification is employed to reduce the rectification loss. Operational principles, large signal modeling, ZVS analysis and design equations are presented. Experimental results demonstrate that the proposed converter can achieve a large ZVS range and significant improvement in efficiency for a 100W (5V, 20A) prototype converter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.398-401
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• 2011

This paper presents a high-efficiency CMOS PWM DC-DC buck converter. It generates a constant output voltage(1-2.8V), from an input voltage(3.4-3.9V). Inductor-based type is chosen and inductor current is controlled with PWM operation. The designed circuit consists of power switch, Pulse Width Generation, Buffer, Zero Current Sensing, Current Sensing Circuit, Clock & Ramp generation, V-I Converter, Soft Start, Compensator and Modulator. Switching Frequency is 1MHz, It operates in CCM when the load current is more than 40mA, and the maximum efficiency is 98.71% at 100mA. Output voltage ripple is 0.98mV(input voltage:3.5V, output voltage:2.5V). The performance of the designed circuit has been verified through extensive simulation using a CMOS $0.18{\mu}m$ technology.