• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.919-929
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• 2014

In recent, the requirements for the safety to the effects of high power electromagnetic wave have been increased along with the development of electricity and electronic equipments. The small sized electronic devices and the various components have been analyzed by using the full-EM simulation and solving a complete set of Maxwell equation. However, the deterministic approach has a drawback and much limitation in the electromagnetic analysis of an electrically large cavity with a high complexity of the structure. In this paper, statistical theory and topological modeling method are combined to analyze the large cavity with a complex structure. In particular, the PWB(Power Balance) method and BLT(Baum-Liu-Tesche) equation are combined and employed to solve the frequency response to the large-scaled cavity with remarkably reduced time-consumption. For instance, a PCB substrate inside box of box are considered as a large structure with a complexity.

• Proceedings of the Safety Management and Science Conference
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• 2007.11a
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• pp.275-298
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• 2007

Recently, all kind of 21C-typed electronic goods show the tendency of hightechnology and digital convergence rapidly. Also, failure mechanism which differs from original goods concept presents. Today, failure mechanism which differs from one that was happened by restricted harmful environment material before adapted the raw of environment material is changing the paradigm of reliability engineering. Thus, when applied the environment matter of original and secondary material at the electronic goods were removed, reliability assessment method and prediction stay into low level. This study suggests as solution to overcome these phenomenon. The study on the management method of environmental restriction substances which is recognized as important element in the reliability assessment about environment material of electronic goods and the study on reliability assessment method of PWB without environment material are progressed.

• Journal of the Korea Safety Management & Science
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• v.9 no.6
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• pp.55-68
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• 2007

Recently, all kind of 21C-typed electronic goods show the tendency of hightechnology and digital convergence rapidly. Also, failure mechanism which differs from original goods concept presents. Today, failure mechanism which differs from one that was happened by restricted harmful environment material before adapted the raw of environment material is changing the paradigm of reliability engineering. Thus, when applied the environment matter of original and secondary material at the electronic goods were removed, reliability assessment method and prediction stay into low level. This study suggests as solution to overcome these phenomenon. The study on the management method of environmental restriction substances which is recognized as important element in the reliability assessment about environment material of electronic goods and the study on reliability assessment method of PWB without environment material are progressed.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1539-1542
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• 2002

In layout of LSI and PWB, block pack- ing problem is very important in order to reduce chip area. Sequence-pair is typical one of conventional pack- ing method and can search nearly-optimal solution by using Simulated Annealing(SA). SA takes huge computation time due to evaluating of various packing results. Therefore, Sequence-pair is not effective enough for fast layout evaluation including estimation of wire length and rotation of every blocks. This paper proposes an efficient block packing method to minimize wire length and chip area. Our method searches an optimal packing efficient- ly by using a cluster growth algorithm with changing the most valuable packing score on packing process.

• Journal of Korean Society for Quality Management
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• v.25 no.2
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• pp.15-27
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• 1997

This paper describes a highly accelerated life test (HALT, USPCBT) method for rapid qualification testing of STH PWB(Silver Through Hole Printed Wiring Boards). This method was carried out to be an alternative to the present time-consuming standard 1344 hours life testing(THB). The accelerated life test conditions were $121^{\circ}C$/95%R.H. at 50V bias and without bias. Their results are compared with those observed in the standard 1344 hours life test at $40^{\circ}C$/95%R.H. at 50V bias and without bias. The studies were focused on the samples time-to-failure as well as the associated conduction and failure mechanisms. The abrupt drop of insulation resistance is due to the absorption of water vapour. And the continuous drop of insulation resistance is due to the Ag migration. The ratios of time-to-failure of HALT(USPCBT) to THB were 25 and 11 at 50V bias and without bias respectively.