• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.166-171
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• 2004

This paper describes a CMOS time to digital converter (TDC) that measures the interval between two signals and converts to a digital signal. There are various methods to measure the time interval. But several architectures have a limitation in resolution and in conversion time. Moreover, they have complex algorithms. But the proposed TDC circuit has achieved a high resolution (25ps) by using a high-speed digital sampler and simple algorithm. The sampler detects when input signals comes into the TDC and output is coded. The proposed multiphase clock generator was also implemented to achieve 25p resolution.

• Journal of Mechanical Science and Technology
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• v.18 no.1
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• pp.92-105
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• 2004

A new algorithm for planning a collision-free path based on algebraic curve is developed and the concept of collision-free Path Space (PS) is introduced. This paper presents a Geometry Mapping (GM) based on two straight curves in which the intermediate connection point is organized in elliptic locus ($\delta$, $\theta$). The GM produces two-dimensional PS that is used to create the shortest collision-free path. The elliptic locus of intermediate connection point has a special property in that the total distance between the focus points through a point on ellipse is the same regardless of the location of the intermediate connection point on the ellipse. Since the radial distance, a, represents the total length of the path, the collision-free path can be found as the GM proceeds from $\delta$=0 (the direct path) to $\delta$=$\delta$$\_$max/(the longest path) resulting in the minimum time search. The GM of elliptic workspace (EWS) requires calculation of interference in circumferential direction only. The procedure for GM includes categorization of obstacles to .educe necessary calculation. A GM based on rectangular workspace (RWS) using Cartesian coordinate is also considered to show yet another possible GM. The transformations of PS among Circular Workspace Geometry Mapping (CWS GM) , Elliptic Workspace Geometry Mapping (EWS GM) , and Rectangular Workspace Geometry Mapping (RWS GM), are also considered. The simulations for the EWS GM on various computer systems are carried out to measure performance of algorithm and the results are presented.

• Structural Engineering and Mechanics
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• v.71 no.1
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• pp.45-56
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• 2019

A modified mechanical model of pre-pressed spring self-centering energy dissipation (PS-SCED) brace is proposed, and the hysteresis band is distinguished by the indication of relevant state variables. The MDOF frame system equipped with the braces is formulated in an incremental form of linear acceleration method. A multi-objective genetic algorithm (GA) based brace parameter optimization method is developed to obtain an optimal solution from the primary design scheme. Parameter sensitivities derived by the direct differentiation method are used to modify the change rate of parameters in the GA operator. A case study is conducted on a steel braced frame to illustrate the effect of brace parameters on node displacements, and validate the feasibility of the modified mechanical model. The optimization results and computational process information are compared among three cases of different strategies of parameter change as well. The accuracy is also verified by the calculation results of finite element model. This work can help the applications of PS-SCED brace optimization related to parameter sensitivity, and fulfill the systematic design procedure of PS-SCED brace-structure system with completed and prospective consequences.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.1
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• pp.11-19
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• 2024

The increased utilization of the FFT in signal processing, cryptography, and various other fields has highlighted the importance of optimization. In this paper, we propose the implementation of an accelerator that processes the radix-2 16 points FFT algorithm more rapidly and efficiently than FFT implementation of existing studies, using FPGA(Field Programmable Gate Array) hardware. Leveraging the hardware advantages of FPGA, such as parallel processing and pipelining, we design and implement the FFT logic in the PL (Programmable Logic) part using the Verilog language. We implement the FFT using only the Zynq processor in the PS (Processing System) part, and compare the computation times of the implementation in the PL and PS part. Additionally, we demonstrate the efficiency of our implementation in terms of computation time and resource usage, in comparison with related works.

• Proceedings of the Optical Society of Korea Conference
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• 2003.02a
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• pp.286-287
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• 2003

Polarization-sensitive optical coherence tomography (PS-OCT) was developed to image highly scattering tissues with accounting for polarization effects in the sample. These polarization-sensitive images can provide additional information on the structure of the tissue because of a polarization state of the light is changed at its interaction with biological tissues. The scattering and birefringence are two phenomena, which change the polarization state of light passing through medium. (omitted)

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.974-977
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• 1999

In this paper, we have proposed the hardware architecture which implements the algorithm for retaining the connectivity which prevents disconnecting in the gray-scale image thinning To perform the image thinning in a real time which find a skeleton in image, it is necessary to examine the connectivity of the skeleton in a real time. The proposed architecture finds the connectivity number in the 4-clock period. The architecture is consists of three blocks, PS(Parallel to Serial) Converter and State Generator and Ridge Checker. The PS Converter changes the 3$\times$3 gray level image to four sets of image pixels. The State Generator examine the connectivity of the central pixel by searching the data from the PS Converter. the 3$\times$3 gray level image determines. The Ridge Checker determines whether the central pixel is on the skeleton or not The proposed architecture finds the connectivity of the central pixel in a 3$\times$3 gray level image in the 4-clocks. The total circuits are verified by the design tools and operate correctly.

• IE interfaces
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• v.13 no.4
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• pp.591-598
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• 2000

In this paper, an efficient algorithm is proposed to find parting lines(PL) and generate parting surfaces(PS) for an injection mold design. We used a Face-Edge Graph which can be made by B-rep information of solid model. The graph is useful for finding the peripheral-loop edges for PL and the inner-loop edges for hole-patch. The PS can be generated automatically by selecting pre-defined direction lines. We can create a core and cavity molds by trimming the raw stock block with the PS and the upper/lower faces of a product model. We implemented proposed method with Unigraphics API functions and C language, and tesed on Unigraphics V15.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6A
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• pp.558-564
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• 2007

3G Long Term Evolution, which aims for various mobile multimedia service provision by enhanced wireless interface, proposes VoIP-based voice service through a Packet Switching (PS) domain. As delay and loss-sensitive VoIP traffic flows through the PS domain, more challenging technical difficulties are expected than in Circuit Switching (CS) domain based VoIP services. Moreover, since 3G LTE, which adopts the OFDM as its physical layer, introduces Physical Resource Block (PRB) as a unit for transmission resources, new types of resource management schemes are needed. This paper proposes a PRB scheduling algorithm of MAC layer for VoIP service in 3G LTE and shows the simulation results. The proposed algorithm has two key parts; dynamic activation of VoIP priority mode to satisfy VoIP QoS requirements and adaptive adjustment of the priority mode duration in order to minimize the degradation of resource utilization.

• Journal of the Korea Computer Industry Society
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• v.6 no.3
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• pp.539-550
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• 2005

The spanning tree, which is being used the most widely in indoor wiring network, is chosen for the network topology of the optimal LAN design. To apply a spanning tree to GA, the concept of $Pr\ddot{u}fer$ numbers is used. $Pr\ddot{u}fer$ numbers can express he spanning tree in an efficient and brief way, and also can properly represent the characteristics of spanning trees. This paper uses Pareto Stratum-Niche Cubicle(PS-NC) GA by complementing the defect of the same priority allowance in non-dominated solutions of pareto genetic algorithm(PGA). By applying the PS-NC GA to the LAN design areas, the optimal LAN topology design in terms of minimizing both message delay time and connection-cost could be accomplished in a relatively short time. Numerical analysis has been done for a hypothetical data set. The results show that the proposed algorithm could provide better or good solutions for the multi-objective LAN design problem in a fairly short time.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.4
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• pp.23-28
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• 2002

In this paper, we have proposed the hardware architecture which implements the algorithm for retaining the connectivity which prevents the disconnection in the gray-scale image thinning. To extract the skeleton from the image in a real time, it is necessary to examine the connectivity of the skeleton in a real time. The proposed architecture finds the connectivity number in the 4-clock period. The architecture consists of three blocks, PS(Parallel to Serial) Converter and Stare Generator and Ridge Checker. The PS Converter changes the 3$\times$3 gray level image to four sets of image pixels. The State Generator examines the connectivity of the central pixel by searching the data from the PS Converter. The Ridge Checker determines whether the central pixel is on the skeleton or not. The proposed architecture finds the connectivity of the central pixel in a 3$\times$3 gray level image in the 4-clocks. The total circuits are verified by the design tools and operate correctly.