• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
• /
• pp.63-66
• /
• 2002

This paper has been studied the parallel resonant inverter which controlling the constant power and tracking the load resonant frequency with PLL is possible, in order to minimize switching losses. The current-fed full-bridge type parallel resonant inverter of an induction heating system was composed of IGBT in switching device. For regulating the output power of an induction heating system, the Fuzzy controller is used. The Fuzzy controller makes the control signal for a stable power regulating control and when reference is changed, it is superior to adaptability. It has been evaluated a stable behavior for a noise with switching and a load disturbance.

• 전기전자학회논문지
• /
• 제22권3호
• /
• pp.716-722
• /
• 2018

This paper presents a voltage angle control strategy for surface permanent magnet synchronous motor (SPMSM) drives used in low-cost applications, wherein a current vector control is not employed. In the proposed method, the current vector control scheme, which requires high precision phase-current sensing units and a fast calculation capability of a motor drive controller, is replaced with the voltage angle controller. The proposed voltage angle controller calculates a d-axis voltage command to make the d-axis current zero by using a simple equation obtained from the voltage equation of SPMSM. The proposed method shows performance similar to the current vector controlled SPMSM drive during steady-states and its structure is very simple and thus it can be easily implemented with a low-cost microcontroller. The effectiveness of the proposed method is verified through simulations and experiments.

• 한국전자파학회:학술대회논문집
• /
• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
• /
• pp.304-308
• /
• 2003

A low cost solution employing harmonic oscillation to the frequency synthesizer at 5.8 GHz is proposed. The proposed frequency synthesizer is composed of 2.9GHz PLL chip, 2.9GHz oscillator, and 5.8GHz buffer amplifier. The measured data shows a frequency tuning range of 290MHz, ranging from 5.65 to 5.94GHz, about 0.5dBm of output power, and a phase noise of -107.67 dBc/Hz at the 100kHz offset frequency. All spurious signals including fundamental oscillation power (2.9GHz) are suppressed at least 15dBc than the desired second harmonic signal.

• 한국전자파학회:학술대회논문집
• /
• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
• /
• pp.269-272
• /
• 2003

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The frequency synthesizer consists of two oscillators - master and slave : A 1.75GHz master oscillator made of PLL synthesizer produces 6th harmonic at 10.5GHz, which excites the following 10.5GHz slave oscillator. The realized frequency synthesizer has a 4.5dBm of output power, and a phase noise of -108dBc/Hz at the 100kHz offset frequency.

• 한국전자파학회:학술대회논문집
• /
• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
• /
• pp.649-659
• /
• 2003

OFDM/FH communication system Is widely used in the wireless communication for the large capacity and high-speed data transmission. However, phase noise and PAPR (peak-to-average power ratio) are the serious problems causing performance impairment. In this paper, PLL (phase locked loop) frequency synthesizer with high switching speed is used for the phase noise model. SSPA and TWTA are considered for the nonlinear HPA model. Under these conditions and by approximating $e^{j{\phi}[m]}$ into $1 + j{\phi}[m]-\frac{1}{2}{\phi}^2[m]$ for the phase noise nonlinear approximation, SINR (signal-to-interference-noise-ratio) with nonlinear HPA and phase noise is derived in the OFDM/FH system. The bit error probabilities (BER) are found by computer simulation method and semi-analytical method. The simulation results closely match with the semi-analytical results.

• 전기학회논문지
• /
• 제57권5호
• /
• pp.889-895
• /
• 2008

In this paper a Fractional-N frequency synthesizer is designed for UHF RFID readers. It satisfies the ISO/IEC frequency band($860{\sim}960MHz$) and is also applicable to mobile RFID readers. A VCO is designed to operate at 1.8GHz band such that the LO pulling effect is minimized. The 900MHz differential I/Q LO signals are obtained by dividing the differential signal from an integrated 1.8GHz VCO. It is designed using a $0.18{\mu}m$ RF CMOS process. The measured results show that the designed circuit has a phase noise of -103dBc/Hz at 100KHz offset and consumes 9mA from a 1.8V supply. The channel switching time of $10{\mu}s$ over 5MHz transition have been achieved, and the chip size including PADs is $1.8{\times}0.99mm^2$.

• Journal of Advanced Marine Engineering and Technology
• /
• 제28권2호
• /
• pp.347-353
• /
• 2004

Neural oscillator can be applied to oscillator systems such as analysis of image information, voice recognition and etc, Conventional learning algorithms(Neural Network or EBPA(Error Back Propagation Algorithm)) are not proper for oscillatory systems with the complicate input patterns because of its too much complex structure. However, these problems can be easily solved by using a synchrony characteristic of neural oscillator with PLL(phase locked loop) function and a simple Hebbian learning rule, Therefore, in this paper, it will introduce an technique for Recognition of the Korean Character using Phase Synchronization Neural Oscillator and will show the result of simulation.

• 한국방송∙미디어공학회:학술대회논문집
• /
• 한국방송공학회 2009년도 IWAIT
• /
• pp.512-515
• /
• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.

• 한국마린엔지니어링학회:학술대회논문집
• /
• 한국마린엔지니어링학회 2005년도 전기학술대회논문집
• /
• pp.1005-1010
• /
• 2005

In this paper, it is presented a frequency modulated continuous wave radar (FMCW) for distance measurement. The frequency range is $10{\sim}11$ GHz and the sweep time of the signal is 100 ms. The test target is 0.8 m2 of metal plate. The experiment is performed in open ground and the pyramidal horn antenna of about 22 dBi gain is used. The beat frequency according to the target moving to 40 m is measured. There is a good agreement between measured and calculated results. But the resolution of the FMCW radar is not good such as about 10 cm. It is result from the nonlinear signal of voltage controlled oscillator (VCO). To improve the nonlinear characteristic of VCO, a high pass filter and phase locked loop (PLL) frequency synthesizer are included in the radar system.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
• /
• pp.1018-1023
• /
• 1998

This paper presents an effective control scheme incorporated in the voltage-fed half-bridge series resonant inverter for induction heating applications, which is based upon a load-adaptive tuned frequency tracking control strategy using PLL(Phase Locked Loop) and its peripheral control circuit. The proposed control strategy ensures a stable operation characteristics of overall inverter system and ZVS(Zero Voltage Switching0 operation in spite of sensitive load parameters variation as well as power regulation, specially in the non-magnetic heating loads. The simulation results and the performance characteristics in the steady-state are shown as compared with the experimental results for a prototype induction cooking system rated at 1.2kW.