• Title/Summary/Keyword: PLL

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An MMIC VCO Design and Fabrication for PCS Applications

  • Kim, Young-Gi;Park, Jin-Ho
    • Journal of Electrical Engineering and information Science
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    • v.2 no.6
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    • pp.202-207
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    • 1997
  • Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.

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Sensor-less Speed Control of PMSM for Driving Oil-free Air Compressor (무급유식 공기압축기 구동을 위한 영구자석 동기 모터의 센서리스 속도제어)

  • Kin, Min Ho;Yang, Oh;Kim, Youn Hyun
    • Journal of the Semiconductor & Display Technology
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    • v.14 no.3
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    • pp.45-50
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    • 2015
  • This paper suggests the sensor-less speed control of PMSM (Permanent Magnet Synchronous Motor) without the position sensor of oil-free air compressor. It estimated d and q axis back electro motive force using Back-EMF (Electro motive Force) observer to control sensor-less speed of PMSM. Also it used the method that tracks the information of rotor position and speed using PLL (Phase Locked Loop) based on estimated d and q axis Back-EMF. The sensor-less speed control of PMSM for oil air compressor application is carried out with the introduced rotor position and speed tracking method. In this paper, the experimental characterization of the sensor-less drive is provided to verify the accuracy of the estimated position and the performance of sensor-less control is analyzed by results obtained from the experiment. Moreover, the potential of PMSM sensor-less drive in industrial application such as compressor drive is also examined.

Software-Based Loran-C Signal Processing (소프트웨어 기반 Loran-C 신호 처리)

  • Im, Jun-Hyuck;Im, Sung-Hyuck;Kim, Woo-Hyun;Jee, Gyu-In
    • Journal of Institute of Control, Robotics and Systems
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    • v.16 no.2
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    • pp.188-193
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    • 2010
  • With GPS being the primary navigation system, Loran use is in steep decline. However, according to the final report of vulnerability assessment of the transportation infrastructure relying on the global positioning system prepared by the John A. Volpe National Transportation Systems Center, there are current attempts to enhance and re-popularize Loran as a GPS backup system through the characteristic of the ground based low frequency navigation system. To advance the Loran system such as Loran-C modernization and eLoran development, research is definitely needed in the field of Loran-C receiver signal processing as well as Loran-C signal design and the technology of a receiver. We have developed a set of Matlab tools, which implement a software Loran-C receiver that performs the receiver's position determination through the following procedure. The procedure consists of receiving the Loran-C signal, cycle selection, calculation of the TDOA and range, and receiver's position determination through the Least Square Method. We experiences the effect of an incorrect cycle selection and various error factors (ECD, ASF, sky wave, CRI, etc.) from the result of the Loran-C signal processing. It is apparent that researches which focus on the elimination and mitigation of various error factors need to be investigated on a software Loran-C receiver. These aspects will be explored in further work through the method such as PLL and Kalman filtering.

A Low Power Fast-Hopping Frequency Synthesizer Design for UWB Applications (UWB 응용을 위한 저전력 고속 스위칭 주파수 합성기의 설계)

  • Ahn, Tae-Won;Moon, Je-Cheol;Kim, Yong-Woo;Moon, Yong
    • 전자공학회논문지 IE
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    • v.45 no.4
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    • pp.1-6
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    • 2008
  • A fast-hopping frequency synthesizer that reduces complexity and power consumption is presented for MB-OFDM UWB applications. The proposed architecture uses 3960 MHz LC VCO, 528 MHz ring oscillator, passive mixer and LC-tuned Q-enhancement BPF to generate Band Group 1 frequencies. The adjacent channel rejection ratio is less than -40 dBc for 3432 MHz and -H dBc for 4488 MHz. A fast switching SCL-tpre MUX is used to produce the required channel output signal and it takes less than 2.2 ns for band switching. The total power consumption is 47.9 mW from a 1.8 V supply.

A CMOS Impulse Radio Ultra-Wideband Receiver for Inner/Inter-chip Wireless Interconnection

  • Nguyen, Chi Nhan;Duong, Hoai Nghia;Dinh, Van Anh
    • Journal of IKEEE
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    • v.17 no.2
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    • pp.176-181
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    • 2013
  • This paper presents a CMOS impulse radio ultra-wideband (IR-UWB) receiver implemented using IBM 0.13um CMOS technology for inner/inter-chip wireless interconnection. The IR-UWB receiver is based on the non-coherent architecture which removes the complexity of RF architecture (such as DLL or PLL) and reduces power consumption. The receiver consists of three blocks: a low noise amplifier (LNA) with active balun, a correlator, and a comparator. Simulation results show the die area of the IR-UWB receiver of 0.2mm2, a power gain (S21) of 12.5dB, a noise figure (NF) of 3.05dB, an input return loss (S11) of less than -16.5dB, a conversion gain of 18dB, a NFDSB of 22. The receiver exhibits a third order intercept point (IIP3) of -1.3dBm and consumes 22.9mW of power on the 1.4V power supply.

Giga-bps CMOS Clock and Data Recovery Circuit with a novel Adaptive Phase Detector (새로운 구조의 적응형 위상 검출기를 갖는 Gbps급 CMOS 클럭/데이타 복원 회로)

  • 이재욱;이천오;최우영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.10C
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    • pp.987-992
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    • 2002
  • In this paper, a new clock and data recovery circuit is proposed for the application of data communication systems requiring ㎓-range clock signals. The circuit is suitable for recovering NRZ data which is widely used for high speed data transmission in ㎓ ranges. The high frequency jitter is one of major performance-limiting factors in PLL, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Futhermore, the phase detector has an adaptive delay cell removing the dead zone problem and has the optimal characteristics for fast locking. The proposed circuit has a convenience structure that can be easily extended to multi-channels. The circuit is designed based on CMOS 0.25㎛ fabrication process and verified by measurement result.

A Hybrid Transceiver for Underwater Acoustic Communication (수중음향 통신을 위한 혼합형 송수신기에 관한 연구)

  • Choi, Young-Chol;Kim, Sea-Moon;Park, Jong-Won;Kim, Seung-Geun;Lim, Yong-Gon;Kim, Sang-Tab
    • Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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    • 2003.05a
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    • pp.319-323
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    • 2003
  • In this paper, we propose a hybrid transceiver for underwater acoustic communication, which allows the system to reduce complexity and increase robustness in time variant underwater channel environments. It is designed in the digital domain except for amplifiers and implemented by using a multiple digital signal processors (DSPs) system. The digital modulation technique is quadrature phase shift keying (QPSK) and frame synchronization is an energy (non-coherent) detection scheme based on the quadrature receiver structure. DSP implementation is based on block data parallel architecture (BDPA). We shaw experimental results in th? underwater anechoic basin at KRISO. The results indicate that the frame synchronization is performed without PLL. Also, we shaw that the adaptive equalizer can compensate frame synchronization error and the correction capability is dependent on the length of equalizer.

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The effects of Pueraria lobata extract on gene expression in liver tissue of rat with estrogen-deficient obesity (갈근이 비만 랫드 간조직의 비만관련 유전자 발현에 미치는 영향)

  • Shin, Yoon Sang;Hwang, Gwi Seo
    • Journal of Society of Preventive Korean Medicine
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    • v.18 no.3
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    • pp.117-128
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    • 2014
  • Objective : It is known that Pueriaria lobata has an anti-osteoporetic effect, anti-cancer effect, anti-pyretic effect, and anti-diabetic effect. The aim of this study was to evaluate anti-obesity effect of Pueriaria lobata extract (PLE), and elucidate the effect of it on gene expression related to lipid metabolism. Method : The experiments were performed with the use of ovariectomized rats as estrogen-deficient obesity model. They were grouped NC (normal control), OC (estrogen-deficient control), PLH (100mg/kg of PLE), PLL (20mg/kg). PLE was orally administered for 6 weeks. Body weights and serum lipid level were estimated, and real-time PCR was performed to investigate the effect of PLE on gene expression in liver. Results : PLE decreased the body weight and serum cholesterol and triglyceride, but increased HDL-cholesterol. And PLE increased leptin, CYP27, CPT1, CYP8B1, ACAT2, LDLR, and SCD1, but reduced $PPAR{\gamma}$, PGC1A, HMG-CoA-R, ACAT1, SCD1, and APoB gene expression in liver tissue of rat with estrogen-deficient obesity. Conclusion : It is concluded that Pueriaria lobata reduced body weight, and its effect was expressed by regulation of gene expression related to lipid metabolism in rats with estrogen-deficient obesity.

A Wideband Clock Generator Design using Improved Automatic Frequency Calibration Circuit (개선된 자동 주파수 보정회로를 이용한 광대역 클록 발생기 설계)

  • Jeong, Sang-Hun;Yoo, Nam-Hee;Cho, Seong-Ik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.2
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    • pp.451-454
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    • 2011
  • In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

A Fast and Robust Grid Synchronization Algorithm of a Three-phase Converters under Unbalanced and Distorted Utility Voltages

  • Kim, Kwang-Seob;Hyun, Dong-Seok;Kim, Rae-Yong
    • Journal of Electrical Engineering and Technology
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    • v.12 no.3
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    • pp.1101-1107
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    • 2017
  • In this paper, a robust and fast grid synchronization method of a three-phase power converter is proposed. The amplitude and phase information of grid voltages are essential for power converters to be properly connected into the utility. The phase-lock-loop in synchronous reference frame has been widely adopted for the three-phase converter system since it shows a satisfactory performance under balanced grid voltages. However, power converters often operate under abnormal grid conditions, i.e. unbalanced by grid faults and frequency variations, and thus a proper active and reactive power control cannot be guaranteed. The proposed method adopts a second order generalized integrator in synchronous reference frame to detect positive sequence components under unbalanced grid voltages. The proposed method has a fast and robust performance due to its higher gain and frequency adaptive capability. Simulation and experimental results show the verification of the proposed synchronization algorithm and the effectiveness to detect positive sequence voltage.