• Journal of the Korea Society for Simulation
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• v.15 no.1
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• pp.11-17
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• 2006

This paper shows a case study of designing a PLC logic simulator that was developed to simulate and verify PLC control programs for nuclear plant systems. The nuclear control system requires strict restrictions rather than normal process control system does, as it works with a high-risky and dangerous nuclear plant. One is that it should assure the safeness of the control programs by exploiting severe testing. The other restriction is that the control programs should be executed fast enough such that they could control multi devices concurrently in real-time. To cope with these restrictions, we devised a logic compiler which generates C-code programs from given PLC logic programs. Once the logic program was translated into C-code, the program could be analyzed by conventional software analysis tools and could be used to construct a fast logic simulator after cross-compiling, in fact, that is a kind of compiled-code simulator.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.8
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• pp.836-844
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• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.1110-1115
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• 1991

Tne mathematical modeling and analysis results of a dataflow logic solving processor(DFLSP) for programmable logic controller(PLC) are proposed in this paper. The logic program language is formalized using a dataflow graph model. From this dataflow graph, the instruction precedence relationship, and deadlock problems, which are major properties of a logic program, are described.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.10
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• pp.5134-5139
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• 2013

Ladder Diagram(LD) or Sequential Function Chart(SFC) is used for the design of complex modern control system with Programmable logic controller(PLC). LD is the most widely utilized among PLC standard language. But recently, SFC is used frequently. SFC is very easy to grasp the sequential flow of control logic but is difficult for describing combinational logic. When the interrupt factor is occurred, the main program is stopped. And after the interrupt program is completed, the main program is restart. Therefore the more complex the interrupt program, the main program is interrupted downtime will be that much longer. In this paper, we propose the method for interrupt implementation without the dwell time of the main program by SFC language and confirm his feasibility through the simulation.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3067-3069
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• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.2
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• pp.365-375
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• 2019

A PLC (Programmable Logic Controller) is a highly-reliable industrial digital computer which supports real-time embedded control applications for safety-critical control systems. Real-time operating systems such as uC/OS have been used for PLCs and must meet real-time constraints. As PLCs have been widely used for industrial control systems and connected to the Internet, they have been becoming a main target of cyberattacks. In this paper, we propose an execution code sanitizer to enhance the security of PLC systems. The proposed sanitizer analyzes PLC programs developed by an IDE before downloading the program to a target PLC, and mitigates security vulnerabilities of the program. Our sanitizer can detect vulnerable function calls and illegal memory accesses in development of PLC programs using a database of vulnerable functions as well as the other database of code patterns related to pointer misuses. Based on these DBs, it detects and removes abnormal use patterns of pointer variables and existence of vulnerable functions shown in the call graph of the target executable code. We have implemented the proposed technique and verified its effectiveness through experiments.

• IE interfaces
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• v.21 no.3
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• pp.294-301
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• 2008

Agile and flexible manufacturing systems make it mandatory that a control program should have features such as agility, flexibility, and reusability in order to run manufacturing unit smoothly. PLCs are the most frequently used control program in manufacturing systems. PLC programs are mostly programmed by subcontraction, which makes correction of code very difficult. As a result, it may cause delay during down time and ramp up time which leads to big loss of revenue and goodwill. To prevent delay during the times, this paper proposes systematic process analysis and application method for programmable logic controller like LLD (Ladder Logic Diagram). The proposed method uses modified human-error investing techniques for documentation and transforming technique to program LLD from the documentation. Furthermore, this paper demonstrates an example of piston mechanism to explain the proposed method.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.4
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• pp.14-19
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• 1998

The purpose of our study is to develop tool kits which give us inexpensive simulation method. We develop a Programmable Logic Controller (PLC) program module with which we can edit and monitor PLC program, a virtual PLC (VPLC) system and simulation equipment. The PLC and simulation equipment are interlinked each other and controlled by the PLC program in real time. So, e can get effect as actural operation. Using our new tool kits we don't have to prepare PLC and machine, because we can configure PLC system and see the response of virtual machine n monitor. For validity of the developed program, we make experiments for the PLC program of elevator and automatic materials weighting system. The experimental results show that the virtual machine (VM) operates properly by the PLC control program.

• Journal of Bio-Environment Control
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• v.4 no.2
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• pp.203-210
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• 1995

Using the programmable logic controller (PLC), a kind of microcomputer, a facility to control EC and pH automatically in nutriculture of tomato was developed. A program for the automatic control of nutriculture was written in ladder diagram language. EC and pH levels of nutrition solution could be maintained at 1.70-1.72 and 6.1-6.5, respectively, during the entire growing period. Better fruits and higher yield were obtained in automatic control plot than in the control plot. Inorganic elements in plant were higher in the former than in the latter.