• Title/Summary/Keyword: PCM(phase change memory)

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A Comparative Study of PRAM-based Join Algorithms (PRAM 기반의 조인 알고리즘 성능 비교 연구)

  • Choi, Yongsung;On, Byung-Won;Choi, Gyu Sang;Lee, Ingyu
    • Journal of KIISE
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    • v.42 no.3
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    • pp.379-389
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    • 2015
  • With the advent of non-volatile memories such as Phase Change Memory (PCM or PRAM) and Magneto Resistive RAM (MRAM), active studies have been carried out on how to replace Dynamic Random-Access Memory (DRAM) with PRAM. In this paper, we study both endurance and performance issues of existing join algorithms that are based on PRAM-based computer systems and have been widely used until now: Block Nested Loop Join, Sort-Merge Join, Grace Hash Join, and Hybrid Hash Join. Our experimental results show that the existing join algorithms need to be redesigned to improve both the endurance and performance of PRAMs. To the best of our knowledge, this is the first research to scientifically study the results of the four join algorithms running on PRAM-based systems. In this work, our main contribution is the modeling and implementation of a PRAM-based simulator for a comparative study of the existing join algorithms.

Electrical Properties of Phase Change Memory Device with Novel GST/TiAlN structure (Novel GST/TiAlN 구조를 갖는 상변화 메모리 소자의 전기적 특성)

  • Lee, Nam-Yeal;Choi, Kyu-Jeong;Yoon, Sung-Min;Ryu, Sang-Ouk;Park, Young-Sam;Lee, Seung-Yun;Yu, Byoung-Gon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.118-119
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    • 2005
  • PRAM (Phase Change Random Access Memory) is well known to use reversible phase transition between amorphous (high resistance) and crystalline (low resistance) states of chalcogenide thin film by electrical Joule heating. In this paper, we introduce a stack-type PRAM device with a novel GST/TiAlN structures (GST and a heating layer of TiAlN), and report its electrical switching properties. XRD analysis result of GST thin film indicates that the crystallization of the GST film start at about $200^{\circ}C$. Electrical property results such as I-V & R-V show that the phase change switching operation between set and reset states is observed, as various input electrical sources are applied.

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Hybrid Memory Adaptor for OpenStack Swift Object Storage (OpenStack Swift 객체 스토리지를 위한 하이브리드 메모리 어댑터 설계)

  • Yoon, Su-Kyung;Nah, Jeong Eun
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.3
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    • pp.61-67
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    • 2020
  • This paper is to propose a hybrid memory adaptor using next-generation nonvolatile memory devices such as phase-change memory to improve the performance limitations of OpenStack-based object storage systems. The proposed system aims to improve the performance of the account and container servers for object metadata management. For this, the proposed system consists of locality-based dynamic page buffer, write buffer, and nonvolatile memory modules. Experimental results show that the proposed system improves the hit rate by 5.5% compared to the conventional system.

The Characteristics of Chalcogenide $Ge_1Se_1Te_2$ Thin Film for Nonvolatile Phase Change Memory Device (비휘발성 상변화메모리소자에 응용을 위한 칼코게나이드 $Ge_1Se_1Te_2$ 박막의 특성)

  • Lee, Jae-Min;Chung, Hong-Bay
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.55 no.6
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    • pp.297-301
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    • 2006
  • In the present work, we investigate the characteristics of new composition material, chalcogenide $Ge_1Se_1Te_2$ material in order to overcome the problems of conventional PRAM devices. The Tc of $Ge_1Se_1Te_2$ bulk was measured $231.503^{\circ}C$ with DSC analysis. For static DC test mode, at low voltage, two different resistances are observed. depending on the crystalline state of the phase-change resistor. In the first sweep, the as-deposited amorphous $Ge_1Se_1Te_2$ showed very high resistance. However when it reached the threshold voltage(about 11.8 V), the electrical resistance of device was drastically reduced through the formation of an electrically conducting path. The phase transition between the low conductive amorphous state and the high conductive crystal]me state was caused by the set and reset pulses respectively which fed through electrical signal. Set pulse has 4.3 V. 200 ns. then sample resistance is $80\sim100{\Omega}$. Reset pulse has 8.6 V 80 ns, then the sample resistance is $50{\sim}100K{\Omega}$. For such high resistance ratio of $R_{reset}/R_{set}$, we can expect high sensing margin reading the recorded data. We have confirmed that phase change properties of $Ge_1Se_1Te_2$ materials are closely related with the structure through the experiment of self-heating layers.

Phase change properties of amorphous $Ge_1Se_1Te_2$ and $Ge_2Se_2Te_5$ chalcogenide thin films. (비정질 $Ge_1Se_1Te_2$$Ge_2Se_2Te_5$ 칼코게나이드박막의 상변화특성)

  • Chung, Hong-Bay;Cho, Won-Ju;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.118-119
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    • 2006
  • In the present work, we investigate the basic physical and thermal properties and electrical resistance change due to phase change in chalcogenide-based $Ge_1Se_1Te_2$ and $Ge_2Se_2Te_5$ thin films. The phase transition from amorphous to crystalline states, and vice versa, of $Ge_1Se_1Te_2$ and $Ge_2Se_2Te_5$ thin films by applying electrical pulses have been studied. The reversible phase transition between the amorphous and crystalline states, which is accompanied by a considerable change in electrical resistivity, is exploited as means to store bits of information.

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Technology of the next generation low power memory system

  • Cho, Doosan
    • International Journal of Internet, Broadcasting and Communication
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    • v.10 no.4
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    • pp.6-11
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    • 2018
  • As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

The Block Swapping Wear leveling Scheme for Storage Class Memory having low endurance (내구도가 낮은 스토리지 클래스 메모리를 위한 블록 교환 마모도 균등화 기법)

  • Lee, HyunKu;Lee, HanNa;Eom, YoungIk
    • Proceedings of the Korea Information Processing Society Conference
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    • 2013.11a
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    • pp.30-32
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    • 2013
  • 현재 차세대 메모리로 불리는 스토리지 클래스 메모리는 빠른 속도, 비휘발성, 바이트 단위 데이터 접근 등의 장점으로 많은 관심을 갖고 있다. 스토리지 클래스 메모리중 하나인 PCM(PhaseChange Memory)은 높은 집적도로 현재 상용화 단계이나 낮은 내구도를 지니고 있어 이를 해결하기 위한 마모도 균등화 기법이 필수적으로 요구된다. 본 논문에서는 마모도 균등화 기법들의 비교 및 분석을 통해 현존하는 마모도 균등화 기법들의 한계를 알아보고 이를 극복하기 위한 새로운 블록 교환 마모도 균등화 기법을 소개한다.