• Journal of electromagnetic engineering and science
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• v.17 no.2
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• pp.105-107
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• 2017

The self-biasing circuit through a feedback resistor is applied to a gallium nitride (GaN) distributed power amplifier (PA) monolithic microwave circuit (MMIC). The self-biasing circuit is a useful scheme for biasing depletion-mode compound semiconductor devices with a negative gate bias voltage, and is widely used for common source amplifiers. However, the self-biasing circuit is rarely used for PAs, because the large DC power dissipation of the feedback resistor results in the degradation of output power and power efficiency. In this study, the feasibility of applying a self-biasing circuit through a feedback resistor to a GaN PA MMIC is examined by using the high operation voltage of GaN high-electron mobility transistors. The measured results of the proposed GaN PA are the average output power of 41.1 dBm and the average power added efficiency of 12.2% over the 6-16 GHz band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.1
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• pp.68-75
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• 2012

The load-insensitivity of the balanced power amplifier(PA) for W-CDMA handset applications is analyzed. The load impedances of the two parallel amplifiers in the balanced PA depending on the output load mismatch are mathematically calculated and with the result, the phase of reflection coefficient at which the linear output power is severely degraded is investigated. From the analysis, we proposed that the linearity of the balanced PA at the phase can be improved by properly increasing the transistor size and thus, multiple balanced PA's with different transistor size are designed and simulated. The simulation result showed that the balanced PA with larger transistor size has improved linear output power under VSWR=4:1.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.10
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• pp.895-902
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• 2012

In this paper, we propose a novel equalizer to compensate for the group delay including AM/PM nonlinear distortion characteristics by the nonlinear power amplifier (PA). The group delay characteristic is a nonlinear non-constant time delay that appears differently depending on each frequency component. The phase distortion by AM/PM characteristics arising from the power amplifier is a major factor to increase group delay. By the group delay distortion, the signal in the constellation expands and is rotated. Considering the problem mentioned above, the nonlinear time delay that appears differently depending on each frequency component is classified as a static group delay and AM/PM characteristic of PA, the different phase transitions depending on the size of input signal as a dynamic group delay. Static group delay estimates and compensate for phase distortions in the frequency domain with type-based method and dynamic group delay compensates for phase rotation in the time domain. We confirmed that the group delay compensation techniques were enough to compensate the group delay characteristics including AM/PM characteristics of the power amplifier.

• Journal of electromagnetic engineering and science
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• v.14 no.3
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• pp.284-292
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• 2014

This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of $0.4-{\mu}m$ and $0.25-{\mu}m$ in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a $0.25-{\mu}m$ transistor. The possibility of using a $0.4-{\mu}m$ transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of $0.4-{\mu}m$ transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the $0.25-{\mu}m$ transistor.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.3
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• pp.437-441
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• 2012

In this paper, we have designed and manufactured 10MHz power source for the application of short distance wireless power transmission. The designed power source consists of a DDS(direct digital synthesizer) signal generator, a buffer driver and a balanced power amplifier. Short range wireless power transmission is usually carried out by near-field inductive coupling between source and load. The distance variation between source and load gives rise to the change of load impedance of power amplifier, which has effect on the operation of power amplifier. To overcome this problem due to load variation of power amplifier, we have adopted the balanced power amplifier using the quadrature hybrid implemented by lumped capacitors and a mutually coupled coil. The experiment results show the above 40dBm output power, frequency range of 9 to 11MHz, and total DC power consumption of 36W.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.2
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• pp.83-90
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• 2000

A simple low-cost and small size 1.88-198 GHz Band RF power amplifier module is developed for IMT2000 repeater. The power amplifier consists of two stage amplifiers that the first stage amplifier is drive amplifier using discrete type P-HEMT (ATF-34143, 800 micron gate width, Agilent Technologies) and the second is power amplifier with 300Bm 1dB gain compression point using GaAs FET(EFA240D-SOT89, 2400 micron gate width, Excelics Semiconductor). this power amplifier module feature a 29.5dBm 1dB gain compression point, 29.5dB gain, 42dBm 3rd order intercept point(OIP3) and -10dB/-l2dB input/output return loss over the 1880-1980 MHz. This PA module is fully integrated using MIC technology into a small size and design by full nonlinear design technologies. The dimensions of this PA module are 42(L) $\times$ 34(W) mm.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.124-127
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• 2005

국내에서는 언제 어디서나 휴대용 단말을 이용하여 저렴한 요금으로 고속의 무선인터넷을 사용할 수 있는 휴대인터넷 서비스를 2006년부터 서비스 할 계획이다. 앞으로 서비스 될 WiBro 휴대인터넷 서비스 방식은 기존 이동통신 방식과 달리 RF 송신 주파수와 수신 주파수가 동일한 TDD (time division duplexing) 방식을 사용한다. WiBro 무선통신 기지국 장비에 있어서도 기존 CDMA 이동통신 기지국 장비에서와 마찬가지로 RF Power Amplifier (PA)가 매우 고가의 핵심 부품이라 할 수 있다. 물론, 기존 FDD (frequency division duplexing) 방식의 CDMA 기지국 PA와 달리 WiBro용 기지국 PA는 TDD 신호를 처리할 수 있는 새로운 기술을 필요로 한다. TDD 방식인 WiBro 기지국용으로 사용할 수 있는 새로운 2.3 GHz 42 W PA를 설계, 제작한 결과를 본 논문에서는 발표하고자 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.802-809
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• 2014

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a $0.18-{\mu}m$ CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.235-245
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• 2014

This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

• Journal of IKEEE
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• v.26 no.3
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• pp.456-461
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• 2022

In this paper, a two-stage single-ended power amplifier (PA) with broadband gain characteristics was presented by utilizing a radio frequency (RF) transformer (TF), which is essential for a differential amplifier. The bandwidth of a PA can be improved by designing TF to have broadband characteristics and then applying it to the inter-stage matching network (IMN) of a PA. For broadband gain characteristics while maintaining the performance and area of the existing PA, an IMN was implemented on an monolithic microwave integrated circuit (MMIC) and a multi-layer printed circuit board (PCB), and the simulation results were compared. As a result of simulating the PA module designed using InGaP/GaAs HBT model, it has been confirmed that the PA employing the proposed design method has an improved fractional bandwidth of 19.8% at a center frequency of 3.3GHz, while the conventional PA showed that of 11.2%.