• Transactions on Electrical and Electronic Materials
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• 제1권3호
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• pp.23-28
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• 2000

A block-oxide layer was formed on the surface of Cu-based leadframe by chamical oxidation method in order to enhance the adhesion strength between Cu-based leadframe and epoxy molding compound (EMC) Using sandwiched double cantilever beam (SDCB) specimens, the adesion strength was measured in terms of interfacial fracture toughness, G$\sub$IC//Results showed that the black-oxide layer was composed of two kinds of layers: pebble-like Cu$_2$O layer and acicular CuO layer, At the initial stage of oxidation the Cu$_2$O layer was preferentially formed and thickened up to around 200 nm whithin 1 minute of the oxidation time. Then the CuO layer started to from atop of the Cu$_2$O layer and thickened up to around 1300 nm until 20 minutes. As soon as the CuO layer formed, the thickness of Cu$_2$O layer began to reduce and finally reached to around 150 nm. The pre-cleaned and the Cu$_2$O coated leadframes showed almost no adhesion of EMC, however, as the CuO precipitates appeared and became continuous, G$\sub$IC/ increased up to around 80 J/㎡. Further oxidation raised G$\sub$IC/ up. to around 100 J/㎡.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.875-877
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• 2007

Zinc tin oxide (ZTO) sol-gel solution was synthesized for ink-jet printable semiconducting ink. Bottom-contact type TFT was produced by printing the ZTO layer between the source and drain electrodes. The transistor involving the ink-jet printed ZTO had the $mobility\;{\sim}\;0.01\;cm^2V^{-1}s^{-1}$. We demonstrated the direct-writing of semiconducting oxide for solution processed TFT fabrication.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.287.2-287.2
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• 2013

We synthesized a new composite of poly sodium 4-styrenesulfonate intercalated graphene oxide for energy storage devices by controlling oxidation time in the synthesis of graphite oxide. Specific capacitance was improved from 20 F/g of the previous composites to 88 F/g of the new composite at the current density of 0.3 A/g. The capacitance retention was 94% after 3000 cycles, indicating that the new composites of high cyclic stability, prominent performance as electric double layer capacitor, and even low resistance could be an excellent carbon based electrode for further energy storage devices.

• 한국재료학회지
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• 제3권4호
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• pp.352-360
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• 1993

열산화막위에 LPCVD법을 이용하여 질화막을 형성시킨 후, 질화막의 열처리 유무와 습식재산화처리의 공정조건에 따른 다양한 막의 두께를 가진 ONO(oxide nitride oxide)캐패시터를 제작하여 여러가지 물성을 조사하였다. 질화막을 습식산화처리하여 전체막의 굴절윷과 식각거동을 관찰한 결과, 40$\AA$두께의 질화막은 치밀하지 못하여 계속되는 산화공정동안에 하부층 산화막이 성장되었고 정전용량의 확보능력도 떨어졌다. ONO다층유전박막의 전도전류는 하부층 혹은 상부층 산화막의 두께가 증가함에 따라 감소하였다. 그러나 산화막이 50$\AA$ 이상인 경우에는 정전용량의 감소요인으로 작용할 뿐, hole유입에 대한 barrier역할은 크게 향상되지 못하였다. 산화전 질화막에 대한 열처리 효과는 막의 굴절율과 정전용량에 큰 영향을 주지 못하였으나 절연파괴전압은 약 2-3V 상승효과를 보였다.

• 한국산학기술학회논문지
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• 제10권7호
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• pp.1489-1496
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• 2009

비정질 인듐-갈륨-아연 산화물 박막트랜지스터를 모델링 하여서, 능동층의 구조, 두께, 평형상태의 전자밀도에 대응하는 박막트랜지스터의 특성을 연구하였다. 단일 능동층 박막트랜지스터의 경우, 능동층이 얇을 때 높은 전계효과이동도를 보였다. 문턱전압의 절대값은 능동층의 두께가 20 nm일 때 최저치를 보였으며, 문턱전압이하 기울기는 두께에 대한 의존성을 보이지 않았다. 복층구조 능동층의 경우, 하부의 능동층이 높은 평형상태 전자밀도를 가질 때보다 우수한 스위칭 특성을 보였다. 이 경우에도 능동층의 두께가 얇을 때에 높은 전계효과 이동도를 보였다. 높은 평형상태 전자밀도의 능동층의 두께를 증가시키면 문턱전압은 음의 방향으로 이동하였다. 문턱전압이하 기울기는 능동층의 구조에 대하여 특별한 의존성을 보이지 않았다. 이상과 같은 데이터는 산화물반도체 박막트랜지스터 능동층의 구조, 두께, 도핑비율을 최적화함에 효과적으로 사용될 것으로 기대된다.

• 한국재료학회지
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• 제11권4호
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• pp.329-334
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• 2001

붕산용액에서 양극산화법으로 장벽형 산화피막을 형성시킨 후 미세조직을 관찰하였다. 양극산화시 인가되는 전압에 따른 피막의 성장속도는 1.54nm/v의 직선적인 관계를 나타냈으며 300v의 인가전압에서 생성된 산화피막의 조직은 50$0^{\circ}C$에서 열처리하였을 경우 피막의 상 전이가 일어나지 않았으나 높은 인가전압에서 생성된 산화피막의 경우는 피막의 조직이 비정질에서 ${\gamma}$-alumina로 변태되는 것이 관찰되었다. 또한 피막이 전자빔 조사에 의해서도 ${\gamma}$-alumina로 전이가 일어났다.

• Transactions on Electrical and Electronic Materials
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• 제11권6호
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• pp.253-256
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• 2010

Different active layer thicknesses for zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were fabricated with a poly-4-vinyphenol polymeric dielectric using injector type atomic layer deposition. The properties of the ZnO TFTs were influenced by the active thickness and width-to-length (W/L) ratio of the device. The threshold voltage of ZnO TFTs shifted positively as the active layer thickness decreased, while the subthreshold slope decreased. The W/L ratio of ZnO TFTs also affected the mobility and subthreshold slope. An optimized TFT structure exhibited an on-tooff current ratio of above 106 with solid saturation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.119-119
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• 2008

The electrical characteristics of Metal-Ferroelectric-Nitride-Oxide-Silicon (MFNOS) structure is studied and compared to the conventional Silicon-Oixde-Nitride-Oxide-Silicon (SONOS) capacitor. The ferroelectric blocking layer is SrBiNbO (SBN with Sr/Bi ratio 1-x/2+x) with the thickness of 200 nm and is fabricated by the RF sputter. The memory windows of MFNOS and SONOS capacitors with sweep voltage from +10 V to -10 V are 6.9 V and 5.9 V, respectively. The effect of ferroelectric blocking layer and charge trapping on the memory window was discussed. The retention of MFNOS capacitor also shows the 10-years and longer retention time than that of the SONOS capacitor. The better retention properties of the MFNOS capacitor may be attributed to the charge holding effect by the polarization of ferroelectric layer.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.316-316
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• 2014

Two different transparent conducting oxide (TCO) layers of Al-doped ZnO (AZO) and $WO_3$ were prepared by a rf sputtering process. Working pressure, deposition time, and target-to-substrate distance were varied for the sputtering process to improve electrical properties of the resulting layer. Thickness of the TCO layers was measured by a profile meter of ${\alpha}$-step. To evaluate the electrical conductivity, surface resistivity of the TCO layers was measured by a four-point probe technique. Decrease of the working pressure resulted in increase of deposition rate and decrease of surface resistivity of the resulting layer. Increase of the layer thickness due to increased deposition time resulted in decrease of surface resistivity of the resulting layer. The shorter the target-to-substrate distance was, the lower was the surface resistivity of the resulting layer.

• 전자공학회논문지D
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• 제34D권6호
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• pp.43-49
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• 1997

Tungsten poycide has studied gate oxide reliability and dielectric strength charactristics as the composition of gate electrode which applied submicron on CMOS and MOS device for optimizing gate electrode resistivity. The gate oxide reliability has been tested using the TDDB(time dependent dielectric breakdwon) and SCTDDB (stepped current TDDB) and corelation between polysilicon and WSi$_{2}$ layer. iN the case of high intrinsic reliability and good breakdown chracteristics on polysilicon, confirmed that tungsten polycide layer is a better reliabilify properities than polysilicon layer. Also, hole trap is detected on the polysilicon structure meanwhile electron trap is detected on polycide structure. In the case of electron trap, the WSi$_{2}$ layer is larger interface trap genration than polysilicon on large POCL$_{3}$ doping time and high POCL$_{3}$ doping temperature condition. WSi$_{2}$ layer's leakage current is less than 1 order and dielectric strength is a larger than 2MV/cm.