• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.1
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• pp.34-40
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• 2006

This paper proposed power system for new DC 49[V] telecommunication using forward three-phase PWM rectifier power factor and efficiency for improvement of ripple voltage. Proposed power system for DC 48[V] telecommunication that consists of power conversion devices including switch, inductor and condenser were made between each line, in power inverter device of each switch control turn-on in period of continuity time control to get power factor '1' of sine wave current and on-off of switch lessens peak current that was happened and got conversion efficiency 92.1[%] composing in PWM rectifier of forward form instead of general PWM rectifier. Also, harmonic input regulation value(IEC61000-3-2 Class-As) satisfy input current and reduce ripple factor of output voltage in state that distortion of three-phase supply is overlapped each other.

• Journal of IKEEE
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• v.14 no.3
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• pp.250-255
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• 2010

The interleaved power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. The buck-boost converter used to provide the high output voltage and low output voltage for portable applications. Also we used the PWM(Pulse Width Modulation) control method for high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The interleaved PMIC to reduce output ripple. And step-down DC-DC converter in stand-by mode below 1mA is designed with LDO in order to achive high efficiency.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.990-991
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• 2015

To drive a magnetron injection gun, thsi paper decribes a design, fabrication and analysis results of proposed compact capacitor charging power supply (CCPS) formed resonant full-bridge inverter for electron gun power supply (EGPS). EGPS needs the -40 kV output voltage and 280 kW output power for few seconds continuously and have to be designed for the rise and fall time to be less than 1 ms with the ripple stability of output voltage of lower than 1%. In order to meet the requirements, we used eight resonant full-bridge modules operated in parallel. Each resonant full-bridge module can supply the current of 0.9 A and the voltage of 40 kV, and is operated by N-phase shift switching pattern. In this paper, we present the design, simulation and test results of interleaved CCPS.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.475-478
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• 2001

In performing the three-level SVPWM, it is nearly impossible to control the neutral-point potential exactly to the half of the dc-link voltage at all times. Therefore the inverter would produce an erroneous output voltage by this voltage unbalance. So the voltage unbalance has to be compensated in doing PWM, when the voltage unbalance occurs whether it is small or large, to make the inverter output voltage follow the reference voltage exactly the same. In this paper, a new compensating method for the neutral-point potential variation in a three-level inverter space vector PWM (SVPWM) is presented. By using the proposed method, the output voltage of the inverter can be made same as the reference voltage and thus the current and torque ripple of the inverter driven motor can be greatly improved even if the voltage unbalance is quite large. The proposed method is verified experimentally with a 3-level IGBT inverter.

• Journal of Electrical Engineering and Technology
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• v.8 no.3
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• pp.507-515
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• 2013

This paper proposes a compensation method for the $2^{nd}$-order harmonic of single-phase grid-connected wind power generation systems. Theoretically, a single-phase grid-connected inverter system has no choice but to cause the $2^{nd}$-order harmonic to DC-link voltage. The reference active current is affected by the DC-link voltage. The output current from the reference active current is distorted by the $1^{st}$ and $3^{rd}$-order harmonic. The proposed method can compensate, conveniently, the reference active current with the $2^{nd}$-order harmonic. To reduce the $2^{nd}$-order ripple in the reference active current, proposed method takes a PR controller as a feed-forward compensator. PR controllers can implement selective harmonic compensation without excessive computational requirements; the use of these controllers simplifies the method. Both the simulation and experimental results agree well with the theoretical analysis.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.126-133
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• 2022

This study proposes a suppression of zero sequence current (ZSC), which is caused by zero sequence voltage (ZSV) for a dual two-level inverter with single DC bus. Large output voltages enable the dual inverter with single DC bus to improve a system efficiency compared with single inverter. However, the structure of dual inverter with single DC bus inevitably generates ZSC, which reduces the system efficiency and causes a current ripple. ZSV is also produced by dead time, and its magnitude is determined by the DC bus and current direction. This study presents a novel space vector modulation method that allows the instantaneous suppression of ZSC. Based on a condition where a switching period is twice a sampling (control) period, the proposed control method is implemented by injecting the offset voltage at the primary inverter. This offset voltage is injected in half of the switching period to suppress the ZSC. Simulation and experiments are used to compare the proposed and conventional methods to determine the ZSC suppression performance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.715-720
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• 2016

This paper proposes a PWM (Pulse Width Modulation) voltage mode DC-DC step-up converter for portable devices. The converter, which is operated with a 1 MHz switching frequency, is capable of reducing the mounting area of passive devices, such as inductor and capacitor, and is suitable for compact mobile products. This step-up converter consists of a power stage and a control block. The circuit elements of the power stage are an inductor, output capacitor, MOS transistors Meanwhile, control block consist of OPAMP (operational amplifier), BGR (band gap reference), soft-start, hysteresis comparator, and non-overlap driver and some protection circuits (OVP, TSD, UVLO). The hysteresis comparator and non-overlapping drivers reduce the output ripple and the effects of noise to improve safety. The proposed step-up converter was designed and verified in Magnachip/Hynix 0.18um 1-poly, 6-metal CMOS process technology. The output voltage was 5 V with a 3.3 V input voltage, output current of 100 mA, output ripple less than 1% of the output voltage, and a switching frequency of 1 MHz. These designed DC-DC step-up converters could be applied to the Personal Digital Assistants(PDA), cellular Phones, Laptop Computer, etc.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.4
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• pp.20-30
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• 2001

A novel 200 MHz CMOS transconductor using translinear cells is proposed. The proposed transconductor consists of voltage followers and current followers based on translinear cells and a resistor. For wide applications, a single-input single-output, a single-Input differential-output, and a fully-differential transconductor are systematically designed, respectively. The theory of operation is described and computer simulation results are used to verify theoretical predictions. The results show that the fully-differential transconductor has a linear input voltage range of ${\pm}2.7$ V, a 3 dB frequency of 200 MHz, and a temperature coefficient of less than 41 $ppm/^{\circ}C$ at supply voltages of ${\pm}3$ V. In order to certify the applicability of the fully-differential transconductor, A ladder-type 3th-order cllitic low pass filter is also designed based on the inductance simulation method. The filter has a ripple bandwidth of 22 MHz, a pass-band ripple of 0.36 dB, and a cutoff frequency of 26 MHz.

• Journal of IKEEE
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• v.23 no.3
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• pp.1104-1107
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• 2019

This paper proposes a DC-DC boost converter for wearable AMOLED display using dead time controller to reduce dead time and improve power efficiency. Also the DC-DC boost converter adopts PWM-SPWM (set-time variable pulse width modulation) dual-mode to enhance power efficiency under light load and decrease output voltage ripple. The proposed circuit has been designed using $0.18{\mu}m$ BCDMOS process. Simulation results show that the circuit has power efficiency of 39%~96% and output ripple voltage of 2 mV under load current range of 1 mA~70 mA. The power efficiency of the proposed circuit is up to 2% higher than the previous PWM-SPWM method and up to 8% higher than only PWM method.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.