• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.14-21
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• 1997

In delay-optimized designs, timing failures due to manufacturing delay defects are more likely to occur because the average timing slacks of paths decrease and the system becomes more sensitive to smaller delay defect sizes. In this paper, the impact of delay optimized logic circuits on delay fault testing will be discussed and compared to the case for non-optimized designs. First, we provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Next we also discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults. Finally, we will give some recommendations on the determination of the system clock time so that the delay-optimized design will have the same manufacturing yield as the non-optimized design and on the determination of delay fault coverage in the delay-optimized design in order to have the same defect-level for delay faults as the non-optimized design, while the system clock time is the same for both designs.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.182-185
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• 2003

Temperature distribution and cooling load in binary current lead are analized, occurring fault current at DC Reactor type superconductor fault current limiter. It is assumed that Normal operating current is 300 A and fault current is 3000 A. Unsteady-state temperature distribution and cooling load of brass current lead optimized for 300 A and 1000 A are calculated by numerical method with TDMA. In the result of calculation, temperature increase in the brass current lead optimized for 300 A is higher than that in the brass current lead optimized for 1000 A, but the temperature increase in the brass current lead optimized for 300 A is not serious. Moreover, increase of cooling load in the brass current lead optimized for 300 A is higher than that in the brass current lead optimized for 1000 A, but normal cooling load in the brass current lead optimized for 300 A is lower than that in the brass current lead optimized for 1000 A. Therefore, designing current lead in superconductor fault current limiter had better to optimize for normal operating current.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.6
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• pp.279-283
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• 2004

In general, triangular shape filters are used in the filter bank when we extract MFCC feature parameters from the spectrum of the speech signal. A different approach, which uses specific filter shapes in the filter bank that are optimized to the spectrum of training speech data, is proposed by Lee et al. to improve the recognition rate. A principal component analysis method is used to get the optimized filter coefficients. Using a large amount of 4-digit telephone speech database, in this paper, we get the MFCCs based on the PCA-optimized filter bank and compare the recognition performance with conventional MFCCs and direct weighted filter bank based MFCCs. Experimental results have shown that the MFCC based on the PCA-optimized filter bank give slight improvement in recognition rate compared to the conventional MFCCs but fail to achieve better performance than the MFCCs based on the direct weighted filter bank analysis. Experimental results are discussed with our findings.

• Journal of The Korean Society of Agricultural Engineers
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• v.46 no.5
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• pp.41-52
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• 2004

In this study, parameters of long and short term runoff model were optimized using genetic algorithm as a basic research for integrated water management in a watershed. In case of Korea where drought and flood occurr frequently, the integrated water management is necessary to minimize possible damage of drought and flood. Modified TANK model was optimized as a long term runoff model and storage-function model was optimized as a short term runoff model. Besides distinguished parameters were applied to modified TANK model for supplementing defect that the model estimates less runoff in the storm period. As a result of application, simulated long and short term runoff results showed 7% and 5% improvement compared with before optimized on the average. In case of modified TANK model using distinguished parameters, the simulated runoff after optimized showed more interrelationship than before optimized. Therefore, modified TANK model can be applied for the long term water balance as an integrated water management in a watershed. In case of storage-function model, simulated runoff in the storm period showed high interrelationship with observed one. These optimized models can be applied for the runoff analysis of watershed.

• Proceeding of EDISON Challenge
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• 2015.03a
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• pp.543-546
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• 2015

There have been subway conflagrations such as Daegu subway conflagration at 2003, Washington D.C conflagration last month and so on. Compared to that, proper evacuation route is far from satisfactory. So this paper suggests optimized route when subway's passengers evacuate from passenger cars. For conducting our experiment, We made temporarily a model of subway station which is made up with 8 passengers cars and 3 exits. Using genetic algorithm, we found the optimized route that first and second passenger cars are optimized to first exit and third, fourth, fifth and sixth passengers cars are optimized to second exit and finally seventh, eighth passengers cars are optimized to third exit. It is expected that real subway station is applied to our experiment by developing passenger distribution algorithm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.169-172
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• 2004

The effect of the process parameters on the stable lifetime in rapid thermal firing(RTF) was investigated in order to optimize the process for the Cz-silicon. The process temperature was varied between $700^{\circ}C\;and\;950^{\circ}C$ while the process time was chosen 1 s and 10 s. At below $850^{\circ}C$ the stable lifetime for 10 s is higher than that for 1 s and increases with increasing by the process temperature. However, at over $850^{\circ}C$ the improved stable lifetime is not dependent on the process time and temperature. On the other hand, two high temperature processes in solar cell fabrics are combined with the optimized process and the non-optimized process. The last process determines the stable lifetime. Also, the degraded stable lifetime could be increased by processing in optimized process. The decreased lifetime can increase using the optimized oxidation process, which is a final process in solar cells. Finally, the optimized and non-optimized processes are applied solar cells.

• International conference on construction engineering and project management
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• 2013.01a
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• pp.163-168
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• 2013

A construction workspace is considered as a critical factor to secure constructability and safety of a project. Specially, optimized size of each workspace helps to minimize any conflicts between workspaces, works and resources within a workspace in the construction site. However, since an existing method for making a decision workspace's size depends on generally experiences of managers and work conditions of activity, it is difficult to perform safe works considering feasible workspace size. The workspace size is changed according to the quantity of resources allocated into each activity as time progresses. Accordingly, it is desirable that optimized workspace size considering input size of resources is determined. To solve these issues, this study configures an optimized model for deciding standard size of workspaces by simple regression analysis and develops a visualized scenario model for simulating the optimized workspace shape in order to support BIM (Building Information Modeling) environment. For this, this study determines an optimized resource shape size considering maximum working radius of each resource and constructs its visual model. Subsequently, input size of resources for each activity is estimated considering safety execution area of resources and workspaces. Based on this, an optimized 3D workspace shape is generated as a VR simulation model of a BIM system based on the suggested methodologies. Moreover, operational feasibility of the developed system is evaluated through a case study for a bride project. Therefore, this study provides a visualized framework so that project managers can establish an efficient workspace planning in BIM environment. Besides, it is expected that constructability, productivity and safety of the project will be improved by minimizing conflicts between workspace and congestions between resources within a workspace in the construction phase.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.66-75
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• 2020

As the increasing expectations of a practical AI (Artificial Intelligence) service makes AI algorithms more complicated, an efficient processor to process AI algorithms is required. To meet this requirement, processors optimized for parallel processing, such as GPUs (Graphics Processing Units), have been widely employed. However, the GPU has a generalized structure for various applications, so it is not optimized for the AI algorithm. Therefore, research on the development of AI processors optimized for AI algorithm processing has been actively conducted. This paper briefly introduces an AI processor especially for inference acceleration, developed by the Electronics and Telecommunications Research Institute, South Korea., and other global vendors for mobile and server platforms. However, the GPU has a generalized structure for various applications, so it is not optimized for the AI algorithm. Therefore, research on the development of AI processors optimized for AI algorithm processing has been actively conducted.

• International Journal of Internet, Broadcasting and Communication
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• v.8 no.1
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• pp.42-52
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• 2016

In this paper, we propose the 16-bits optimization design of the ARIA block-cipher algorithm for embedded systems with 16-bits processors. The proposed design adopts 16-bits XOR operations and rotated shift operations as many as possible. Also, the proposed design extends 8-bits array variables into 16-bits array variables for faster chained matrix multiplication. In evaluation experiments, our design is compared to the previous 32-bits optimized design and 8-bits optimized design. Our 16-bits optimized design yields about 20% faster execution speed and about 28% smaller footprint than 32-bits optimized code. Also, our design yields about 91% faster execution speed with larger footprint than 8-bits optimized code.

• Journal of Power Electronics
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• v.14 no.5
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• pp.937-945
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• 2014

This paper presents an optimized space vector pulse-width modulation (OSVPWM) technique for a five-level cascaded H-bridge (CHB) inverter. The space vector diagram of the five-level CHB inverter is optimized by resolving it into inner and outer two-level space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the five-level CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulse-width modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 field-programmable gate array from Xilinx, Inc. The experiment results are then presented for verification.