• 제목/요약/키워드: Optimal Buffer Size

검색결과 43건 처리시간 0.025초

하모니서치 알고리즘을 이용한 반도체 공정의 최적버퍼 크기 결정 (Determination of Optimal Buffer Size for Semiconductor Production System using Harmony Search Algorithm)

  • 이병길;변민석;김여진;이종환
    • 반도체디스플레이기술학회지
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    • 제19권4호
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    • pp.39-45
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    • 2020
  • In the production process, the buffer acts as a buffer to alleviate some of the problems such as delays in delivery and process control failures in unexpected situations. Determining the optimal buffer size can contribute to system performance, such as increased output and resource utilization. However, there are difficulties in allocating the optimal buffer due to the complexity of the process or the increase in the number of variables. Therefore, the purpose of this research is proposing an optimal buffer allocation that maximizes throughput. First step is to design the production process to carry out the research. The second step is to maximize the throughput through the harmony search algorithm and to find the buffer capacity that minimizes the lead time. To verify the efficiency, comparing the ratio of the total increase in throughput to the total increase in buffer capacity.

Buffer Scheme Optimization of Epidemic Routing in Delay Tolerant Networks

  • Shen, Jian;Moh, Sangman;Chung, Ilyong;Sun, Xingming
    • Journal of Communications and Networks
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    • 제16권6호
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    • pp.656-666
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    • 2014
  • In delay tolerant networks (DTNs), delay is inevitable; thus, making better use of buffer space to maximize the packet delivery rate is more important than delay reduction. In DTNs, epidemic routing is a well-known routing protocol. However, epidemic routing is very sensitive to buffer size. Once the buffer size in nodes is insufficient, the performance of epidemic routing will be drastically reduced. In this paper, we propose a buffer scheme to optimize the performance of epidemic routing on the basis of the Lagrangian and dual problem models. By using the proposed optimal buffer scheme, the packet delivery rate in epidemic routing is considerably improved. Our simulation results show that epidemic routing with the proposed optimal buffer scheme outperforms the original epidemic routing in terms of packet delivery rate and average end-to-end delay. It is worth noting that the improved epidemic routing needs much less buffer size compared to that of the original epidemic routing for ensuring the same packet delivery rate. In particular, even though the buffer size is very small (e.g., 50), the packet delivery rate in epidemic routing with the proposed optimal buffer scheme is still 95.8%, which can satisfy general communication demand.

Lifetime Maximization of Wireless Video Sensor Network Node by Dynamically Resizing Communication Buffer

  • Choi, Kang-Woo;Yi, Kang;Kyung, Chong Min
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제11권10호
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    • pp.5149-5167
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    • 2017
  • Reducing energy consumption in a wireless video sensor network (WVSN) is a crucial problem because of the high video data volume and severe energy constraints of battery-powered WVSN nodes. In this paper, we present an adaptive dynamic resizing approach for a SRAM communication buffer in a WVSN node in order to reduce the energy consumption and thereby, to maximize the lifetime of the WVSN nodes. To reduce the power consumption of the communication part, which is typically the most energy-consuming component in the WVSN nodes, the radio needs to remain turned off during the data buffer-filling period as well as idle period. As the radio ON/OFF transition incurs extra energy consumption, we need to reduce the ON/OFF transition frequency, which requires a large-sized buffer. However, a large-sized SRAM buffer results in more energy consumption because SRAM power consumption is proportional to the memory size. We can dynamically adjust any active buffer memory size by utilizing a power-gating technique to reflect the optimal control on the buffer size. This paper aims at finding the optimal buffer size, based on the trade-off between the respective energy consumption ratios of the communication buffer and the radio part, respectively. We derive a formula showing the relationship between control variables, including active buffer size and total energy consumption, to mathematically determine the optimal buffer size for any given conditions to minimize total energy consumption. Simulation results show that the overall energy reduction, using our approach, is up to 40.48% (26.96% on average) compared to the conventional wireless communication scheme. In addition, the lifetime of the WVSN node has been extended by 22.17% on average, compared to the existing approaches.

동영상 재생 품질 향상을 위한 최적 버퍼 수준 결정 (Estimating the Optimal Buffer Size on Mobile Devices for Increasing the Quality of Video Streaming Services)

  • 박현민
    • 한국콘텐츠학회논문지
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    • 제18권3호
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    • pp.34-40
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    • 2018
  • 본 연구에서는 모바일 단말에서 재생되는 동영상 서비스의 끊김 현상을 방지할 수 있는 최적의 버퍼 크기를 산정하고자 한다. 버퍼는 VOD서비스를 위해 수신 단말에 도착한 멀티미디어 패킷의 저장 공간을 의미한다. 만약 버퍼 크기가 너무 크면, 재생 서비스 시작 전의 지연시간이 길어지게 된다. 반대로 버퍼 크기가 너무 작은 경우, 수신 단말에 도착한 패킷의 부족으로 재생 서비스가 중간에 멈출 수 있다. 그러므로 적정 버퍼 크기는 모바일 단말에서의 재생 서비스 품질 척도가 될 수 있다. 본 연구에서는 재생 서비스의 버퍼링 과정을 이산시간 대기행렬로 모델링한다. N정책을 갖는 Geo/G/1 대기행렬에서 바쁜기간의 평균길이와 평균 대기시간을 분석한다. 또한 도출된 성능척도를 이용하여 모바일 단말에서의 최적의 버퍼 크기를 결정하는 수치예제를 제시한다. 본 연구 결과를 이용하여 재생 도중의 끊김 현상 방지와 재생 시작 초기의 지연시간 최소화를 달성하여 이용자 만족도를 높일 수 있을 것이다.

Energy-efficient Buffer-aided Optimal Relay Selection Scheme with Power Adaptation and Inter-relay Interference Cancellation

  • Xu, Xiaorong;Li, Liang;Yao, Yingbiao;Jiang, Xianyang;Hu, Sanqing
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제10권11호
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    • pp.5343-5364
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    • 2016
  • Considering the tradeoff between energy consumption and outage behavior in buffer-aided relay selection, a novel energy-efficient buffer-aided optimal relay selection scheme with power adaptation and Inter-Relay Interference (IRI) cancellation is proposed. In the proposed scheme, energy consumption minimization is the objective with the consideration of relay buffer state, outage probability and relay power control, in order to eliminate IRI. The proposed scheme selects a pair of optimal relays from multiple candidate relays, denoted as optimal receive relay and optimal transmit relay respectively. Source-relay and relay-destination communications can be performed within a time-slot, which performs as Full-Duplex (FD) relaying. Markov chain model is applied to analyze the evolution of relay buffer states. System steady state outage probability and achievable diversity order are derived respectively. In addition, packet transmission delay and power reduction performance are investigated with a specific analysis. Numerical results show that the proposed scheme outperforms other relay selection schemes in terms of outage behavior with power adaptation and IRI cancellation in the same relay number and buffer size scenario. Compared with Buffer State relay selection method, the proposed scheme reduces transmission delay significantly with the same amount of relays. Average transmit power reduction can be implemented to relays with the increasing of relay number and buffer size, which realizes the tradeoff between energy-efficiency, outage behavior and delay performance in green cooperative communications.

EFFECT OF THE NUMBER OF ACTIVE SOURCES ON ABR BUFFER SIZE

  • Lee, Yu-Tae;Han, Dong-Hwan
    • Journal of applied mathematics & informatics
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    • 제7권3호
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    • pp.861-873
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    • 2000
  • Rate-based flow control plays an important role for efficient traffic management of Available Bit Rate(ABR) services. We deal with the problem of the buffer dimension for rate-based ABR control. In this paper, we analyze the Allowed Cell Rate(ACR) of a source and the queue size in a steady state. First, we investigate the effect of the number of active sources on the behavior of the ACR and the maximum queue size. Reflecting the effect of this real scenes, we determine the optimal buffer size and buffer threshold. Furthermore, our analytic results are compared with the case when the effect of the number of active sources is disregarded.

제약자원 버퍼의 최적 크기 결정 (Optimal size of the constraint buffer in TOC)

  • 고시근
    • 한국경영과학회:학술대회논문집
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    • 대한산업공학회/한국경영과학회 2002년도 춘계공동학술대회
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    • pp.476-480
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    • 2002
  • The theory of constraints (TOC) has become a valuable system in modern operations management. Using the ideas and methods of the TOC, companies can achieve a large reduction of work-in-process and finished-goods inventories, significant improvement in scheduling performance, and substantial earnings increase. The purpose of this paper is to calculate the optimal size of the time buffer which is used to accommodate disruptions in production processes and provide maximum productivity of capacity constrained resources. After the problem formulation in terms of single server queueing model, we observed the system behavior by sensitivity analyses.

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시뮬레이션 모델 구축과 분석을 통한 솔레노이드 생산라인의 최적 버퍼 할당 (Optimal buffer allocation of the solenoid production line using simulation)

  • 김영진;노상도;문정환
    • 한국시뮬레이션학회논문지
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    • 제17권4호
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    • pp.51-60
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    • 2008
  • 본 논문의 목적은 생산성 향상을 위한 시뮬레이션 모델의 구축과 활용으로, 자동차 솔레노이드 밸브를 생산하는 국내의 한 중소기업을 대상으로 최적 버퍼 할당 문제를 시뮬레이션을 통하여 해결하였다. 이를 위하여 생산 라인을 구성하고 있는 주요 요소나 운영 정책 등이 변화했을 때 이러한 변화가 생산량에 어떠한 영향을 주는지를 확인 할 수 있도록 생산 라인의 공정과 작업 내용 및 순서, 공정 수행시간, 총 근무 시간, 가동률, 작업 효율, 불량률, 재공재고 등을 주요 입력 변수로 설정하였으며, 실제 생산라인 운영 결과와의 비교를 통해 이를 검증하였다. 본 논문에서 대상으로 한 솔레노이드 생산라인은 공정 중의 버퍼가 지나치게 많은 상황이지만, 버퍼를 줄이게 되면 결품 발생으로 생산이 중단되는 경우가 발생하기 때문에 많은 양의 버퍼를 유지하고 있었다. 본 논문에서는 이러한 문제를 해결하기 위하여, 시뮬레이션 모델을 구성, 검증하고 이를 활용하여 생산에 영향을 미치지 않는 최적의 버퍼 값을 결정 하였다. 본 본문에서 구축된 시뮬레이션 모델은 생산 라인에 영향을 미치는 많은 요소들을 입력 요소로 고려할 수 있도록 구성되었으며, 최적 버퍼 할당 뿐 아니라, 다양한 목적의 분석에 활용이 가능하다.

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이중 NAND 플래시 구조의 버퍼시스템에서 효율적 버퍼 크기 (The Efficient Buffer Size in A Dual Flash Memory Structure with Buffer System)

  • 정보성;이정훈
    • 대한임베디드공학회논문지
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    • 제6권6호
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    • pp.383-391
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    • 2011
  • As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.

최소 delay를 갖는 buffer 회로의 설계 (A Design of The Buffer Circuit having Minimum Delay Time)

  • 강인엽;송민규;김원찬
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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    • pp.1512-1515
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    • 1987
  • The buffer circuit having minimum delay time is designed and analyzed in this paper. Considering the parasitic components of the MOS transistor, the optimal transistor size ratio between the individual buffer stages is presented. This paper's result is better than that of the Mead and Conway's analysis [1] with respect to both delay time and total area that buffer occupies.

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