• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.485-487
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• 1999

We propose the algorithm with which one can solve the problem of the two-level hierarchical optimal control of nonlinear systems by repeatedly updating the state vectors using the haar function and Picard's iteration methods. Using the simple operation of the coefficient vectors from the fast haar transformation in the upper level and applying that vectors to Picard iteration methods in the independently lower level allow us to obtain the another method except the inversion matrix operation of the high dimention and the kronecker product in the optimal control algorithm.

• 제어로봇시스템학회:학술대회논문집
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• 1994.10a
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• pp.763-768
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• 1994

A hierarchical Petri- net is utilized in supervising an automated vehicle system, The supervisory system is supported by computer networking in order to facilitate necessary processing, and consists of control flow level and computer allocation level so that a designer and an operator can easily build and/or access to each level. There are two modes of utilizing Petri net here in this paper. One is to employ it in designing the control system, in order to optimally allocate computers in every stage of processing. The other is for supervision of the system in operation, in order for the operator to be in a easy-to-comprehend environment of operation. The effect of these two modes of utilizing Petri net is examined.

• Journal of Engineering Education Research
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• v.23 no.4
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• pp.66-75
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• 2020

This study was conducted using the literature review and survey research to analyze the operational status and effectiveness of the single-track accredited program, which has been mandatory since 2016. The research targets to achieve the purpose of the study were the nationwide engineering education accreditation system operating colleges, departments, and engineering education innovation centers. Finally, 183 copies were collected from faculty members at 69 colleges and 554 copies at the department level. As a result of the survey, the college recognized more positively about the operation of the single-track accredited program, and more than 50% of respondents said that there were difficulties due to the operation of the system. The contents required were analyzed and presented. Based on this, the engineering education accreditation system, including the single-track accredited program, suggested the direction of support at the government level and the ABEEK level to better settle down in the field of engineering colleges.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.4
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• pp.235-242
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• 2016

The emerging High-Efficiency Video Coding (HEVC) standard attempts to improve coding efficiency by a factor of two over H.264/Advanced Video Coding (AVC) at the expense of an increase in computational complexity. Mode decision with motion estimation (ME) is still one of the most time-consuming computations in HEVC, as it is with H.264/AVC. Thus, fast mode decisions are not only an important issue to be researched, but also an urgent one. Several schemes for fast mode decisions have been presented in reference software and in other studies. However, the conventional hierarchical mode decision can be useless when block-level parallelism is exploited. This paper proposes operation-level exploration that offers more chances for early termination. An early termination condition is checked between integer and fractional MEs and between the parts of one partition type. The fast decision points of the proposed algorithm do not overlap those in previous works. Thus, the proposed algorithms are easily used with other fast algorithms, and consequently, independent speed-up is possible.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.19-33
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• 2002

In this Paper, we described the Parwan CPU using a VHDL at the behavioral level and then described by connecting CPU components at the dataflow level. Finally, we simulated to verify of execution of a CPU processor using a test-bench method. A presented design method was to enable information exchange of design and representation of operation were very exact and simple. Also. a documentation of design was available and it was easy that verify a operation of designed processor. The behavioral description of VHDL aids designer as we verify our understanding of the designed system, while the dataflow description can be used to verify the bussing and register structure of the design.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.6
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• pp.509-516
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• 2015

The overmodulation characteristics of a carrier-based medium vector pulse width modulation (CBMVPWM) are examined in this study. CBMVPWM can completely eliminate leakage currents in a three-phase, three-level inverter using only the switching states with the same common mode voltage even in an overmodulation operation. The analytic equations for the magnitude of the output voltage and the switching frequency are derived for overmodulation operation, and the effect of dead time on the leakage current is demonstrated. This study presents the operating principle of CBMVPWM, basic overmodulation features, and simulations and experiments for operating verification.

• Journal of Power Electronics
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• v.16 no.1
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• pp.93-101
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• 2016

A new four-primary-switch diode clamped soft switching three-level DC-DC converter (TLDC) with full zero-voltage switching (ZVS) load range and TL secondary voltage waveform is proposed. The operation principle and characteristics of the presented converter are discussed, and experimental results are consistent with theoretical predictions. The improvements of the proposed converter include a simple and compact primary structure, TL secondary rectified voltage waveform, wide load range ZVS for all primary switches, and full output-regulated range with soft switching operation. The proposed converter also has some disadvantages. The VA rating of the transformer is slightly larger than that of conventional TLDCs in variable input and constant output mode. The conduction loss of the primary coil is slightly higher because an air gap is inserted into the magnetic cores of the transformer. Finally, the secondary circuit is slightly complex.

• The Transactions of the Korean Institute of Power Electronics
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• v.28 no.1
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• pp.1-7
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• 2023

A grid-connected 3-level NPC inverter is a power conversion device that connects renewable energy generators, such as photovoltaic or wind turbines to the grid. Although many studies have focused on this inverter, commercializing it requires strictly satisfying various safety and power quality-related standards. Among many standards, leakage current and grid current total harmonic distortion(THD) can be affected by external factors such as installation environment, aging, and grid conditions. Hence, inverter operations that can satisfy these standards need to be explored. In this study a 3-level NPC inverter operation algorithm using the Phase Opposition Disposition-PWM method that can effectively reduce leakage current and switching frequency adjustment to reduce THD effectively has been proposed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.10-27
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• 2005

In this paper, we propose a high level design architecture of WCDMA(UMTS) base station modem and synchronization algorithms applied to the proposed architecture. Also analysis of each synchronization algorithm and performance evaluation of fixed point designed modem are shown. Since the target system is base station modem, each synchronization algorithm is designed for its stable operation. To minimize implementation complexity, optimum fixed point design for best operation of synchronization algorithms is performed. We performed symbol level link simulation with fixed point designed modem simulator for data rate of 12.2kbps, 64kbps, 144kbps, and 384kbps. We compared performance results to the minimum requirements specified in 3GPP TS 25.104(Release 5). Extensive computer simulation shows that the proposed modem architecture has stable operation and outperform the minimum requirement by 2 dB. The proposed modem architecture has been applied in the implementation of WCDMA reverse link receiver modem chip successfully.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1318-1328
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• 2015

The photovoltaic (PV) power conditioning system for small-scale applications has gained significant interest in the past few decades. However, the standalone mode of operation has been rarely approached. This paper presents a two-stage multi-level micro-inverter topology that considers the different operation modes. A multi-output flyback converter provides both the DC-Link voltage balancing for the multi-level inverter side and maximum power point tracking control in grid connection mode in the PV stage. A modified H-bridge multi-level inverter topology is included for the AC output stage. The multi-level inverter lowers the total harmonic distortion and overall ratings of the power semiconductor switches. The proposed micro-inverter topology can help to decrease the size and cost of the PV system. Transient analysis and controller design of this micro-inverter have been proposed for stand-alone and grid-connected modes. Finally, the system performance was verified using a 120 W hardware prototype.