• Title/Summary/Keyword: Op-Amp

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A 8-bit Variable Gain Single-slope ADC for CMOS Image Sensor

  • Park, Soo-Yang;Son, Sang-Hee;Chung, Won-Sup
    • Journal of IKEEE
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    • v.11 no.1 s.20
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    • pp.38-45
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    • 2007
  • A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

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A Rail-to-Rail CMOS Op-amp with Constant Gain by Using Output Common Mode Current Compensation (출력 단 공통모드 전류 보상으로 일정한 이득을 갖는 Rail-to-Rail CMOS 연산증폭기)

  • Lee, Dong-Geon;Jeong, Hang-Geun
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.457-458
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    • 2008
  • This paper presents an output common mode current compensation method to achieve both constant Gm and constant gain. A conventional rail-to-rail CMOS op-amp with constant Gm was designed by using complementary differential input stage and current compensation skills. But it doesn't operate constant gain, because of output resistance variation. With $0.18{\mu}m$ CMOS process, the simulation results show that the differential gain variation can achieve less than 1.3dB. And a 60dB gain, a 13.5MHz unity gain-frequency, and 1mW power consumption, when operating at 1.8V and 10pF load.

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A 1.5V CMOS High Frequency Operational Amplifier for High Frequency Signal Processing Systems. (고주파 신호처리 시스템을 위한 1.5V CMOS 고주파 연산증폭기)

  • 박광민;김은성;김두용
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1117-1120
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    • 2003
  • In this paper, a 1.5V CMOS high frequency operational amplifier for high frequency signal processing systems is presented. For obtaining the high gain and the high unity gain frequency with the 1.5V supply voltage, the op-amp is designed with simple two stages which are consisting of the rail-to-rail differential input stage and the class-AB output stage. The designed op-amp operates with the 1.5V supply voltage, and shows well the push-pull class-AB operation. The simulation results show the DC open loop gain of 77dB and the unity gain frequency of 100MHz for the 1㏁ ┃ 10pF load. When the resistive load R$_1$. is varied from 1㏁ to 1 ㏀, the DC open loop gain decreases by only 4dB.

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Design of Low-Power TFT-LCD Source Driver

  • Sung, Yoo-Chang;Choi, Byong-Deok;Kwon, Oh-Kyong
    • 한국정보디스플레이학회:학술대회논문집
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    • 2000.01a
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    • pp.17-18
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    • 2000
  • A low-power source driver for TFT-LCDs has been proposed using the triple charge sharing method that enhances the AC power saving efficiency of the prior charge sharing method. The AC power saving efficiency of the proposed source driver reaches 66.6%. In addition, a novel OP-AMP with low-quiescent current has been developed. The measured quiescent current of the OP-AMP is $5{\mu}A{\sim}7{\mu}A$ at VDD=5V and VSS=0V with load resistance of $2k{\Omega}$ and load capacitance of 300pF.

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A power-reduction technique and its application for a low-voltage CMOS operational amplifier (저전압용 CMOS 연산 증폭기를 위한 전력 최소화 기법 및 그 응용)

  • 장동영;이용미;이승훈
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.6
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    • pp.37-43
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    • 1997
  • In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

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A Study on the Protection Circuit of Electronic Starter for Fluorescent Lamps of end-of-life (전자식 스타터의 램프수명말기 보호 회로)

  • 신상욱;이진우
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.12 no.4
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    • pp.1-5
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    • 1998
  • This paper reports the developement of the protection circuit of electronic starter for fluorescent lamps of end-of-life. The key point of this paper is to protect for lamp of end-of-life by four operational amplifiers (OP AMP) and one solid state relay (SSR). In this paper we simulated the circuit by PSpice and compared with experimental results.

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A Study on the Low-Pass Filter Design Using the Concept of FDNR (FDNR개념을 이용한 저역Filter에 관한 연구)

  • 이성백;김인재
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.7 no.1
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    • pp.29-36
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    • 1982
  • This paper investigates the utilization of the concept of FDNR first proposed by L. T. Bruton to eliminate the necessity of inductance in a network. A new FDNR with single OP-Amp is also introduces to simplify the network in this paper. The efficiency of the new contrivance is also proved through experimented confirmation of its frequency when applied to on active eliptic low pass filter.

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Design of power amplifier and antenna for wireless power transmission in 125kHz (125kHz대에서 무선전력전송을 위한 전력증폭기와 송수신 Antenna 설계)

  • Im, Sang-Uk;Kim, Yong-Sang;Kim, Do-Hun;Kim, Yang-Mo
    • Proceedings of the KIEE Conference
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    • 2003.11b
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    • pp.27-30
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    • 2003
  • Wireless power transmission system is one of the very interesting field not only in a technical and economical point of view but also that people are still trying to realize lossless power transmission. This paper has a purpose on the efficient power transmission at the passive type ICcard by using wireless power transmission system. The most difficult but important part of the passive type RF-ID system is building the system that supplies power from Reader-antenna to IDcard-antenna. To check what is the most efficient way to deliver power depending on what kind of specifications of the power-amp in reader, antenna and antenna in IDcard is for operating IDcard circuit efficiently receiving the power from reader-antenna. For this, we used 125kHz sinewave for RF signal as a basic specification, power-amp : OP-Amp for amplifying signal and AB Class push-pull power-amp for amplifying power, loop type antenna.

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Effects of Herba Cirsii Extracts on Glucose Uptake in OP9 Cells (OP9 세포에서 포도당 흡수능에 대한 대계 추출물의 효과)

  • Kim, Mi Seong;Song, Je Ho
    • Journal of Physiology & Pathology in Korean Medicine
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    • v.28 no.2
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    • pp.195-199
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    • 2014
  • Although the Herba Cirsii is known to posses beneficial health effects, the anti-diabetic effects and the mechanism of action have not been elucidated. In the present study we have shown that Herba Cirsii Extract (HCE) can stimulate glucose uptake in OP9 adipocytes. Unlike insulin, HCE did not stimulate the Ser473 phosphorylation and activation of Akt. The increasing effects of HCE on glucose uptake were inhibited by PD680509 and compound C pretreatment, which means that the glucose uptake effects by HCE were carried out by extracelluar signal-regulated kinase1/2(ERK1/2) and AMP-activated protein kinase (AMPK) activation. Further studies revealed that HCE stimulated glucose transport occurs through a mechanism involving ERK1/2 activation and AMPK activation.

Study on the Development of Linearity of Broad-Band SDLVA Using Clamping Op-Amp (Clamping Op-Amp를 이용한 광대역 로그 비디오 증폭기의 선형성 개선에 관한 연구)

  • Park, Jong-Sul;Kim, Jong-Geon;Kim, Jum-Sik
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.6
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    • pp.641-647
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    • 2011
  • This paper describes a design and fabrication of SDLVA. The SDLVA operates 0.5~2.0 GHz with -70~0 dBm dynamic range. The SDLVA is consisted of 5-stage RF block, 2-stage detector block and summation circuit using clamping op-amp to improve video linearity. The result of measure, SDLVA of RF path has over 73 dB small-signal gain and 10.1~12.2 dBm saturation power. The video path has 25 mV/ dB${\pm}$1.0 mV and under ${\pm}$1.5 dB video linearity.