• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.6-13
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• 2009

For X-band phased array systems, a power amplifier, a 6-bit phase shifter, a 6-bit digital attenuator, and a SPDT transmit/receive (T/R) switch are fabricated and measured. All circuits are demonstrated by using CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascade structures. It provides 1-dB gain-compressed output power ($P_{1dB}$) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8-11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of nMOS transistors as a switch and meandered microstrip lines for desired inductances. It has $360^{\circ}$ phase-control range and $5.6^{\circ}$ phase resolution. At 8-11 GHz frequencies, it has RMS phase and amplitude errors are below $5^{\circ}$ and 0.8 dB, and insertion loss of $-15.7\;{\pm}\;1,1\;dB$. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employes compensation circuits for low insertion phase variation. It has max. attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and $2^{\circ}$ at 8-11 GHz frequencies, and insertion loss is $-10.5\;{\pm}\;0.8\;dB$. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of -1.5 dB, return loss below -15 dB, and isolation about -30 dB. The fabricated chip areas are $1.28\;mm^2$, $1.9mm^2$, $0.34\;mm^2$, $0.02mm^2$, respectively.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.512-522
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• 2003

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1288-1298
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• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.

• The Korean Journal of Air & Space Law and Policy
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• v.32 no.2
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• pp.155-188
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• 2017

On the one hand, the 4th Industrial Revolution provides a positive opportunity to build a new civilization paradigm for mankind. However, on the other hand, due to the 4th Industrial Revolution, artificial intelligence such as 'Goggle Alpha Go' revolutionized and even the human ability was replaced with a 'Silicon Chip' as the opportunity to communicate decreases, the existence of human beings is weakened. And there is a growing concern that the number of violent crimes, such as psychopath, which hunts humans as games, will increase. Moreover, recent international terrorism is being developed in a form similar to 'Psychopathic Violent-Crime' that indiscriminately attacks innocent people. So, the probability that terrorist organizations abuse the positive effects provided by the Fourth Industrial Revolution as means of terrorism is increasing. Therefore, the paradigm of aviation terrorism is expected to change in a way that attacks airport facilities and users rather than aircraft. Because airport facilities are crowded, and psychopathic terrorists are easily accessible. From this point of view, our counter terrorism system of aviation has many weak points in various aspects such as: (1) limitations of counter-terrorism center (2) inefficient on-site command and control system (3) separated organization for aviation security consultation (4) dispersed information collection function in government (5) vulnerable to cyber attack (6) lack of international cooperation network for aviation terrorism. Consequently, it is necessary to improve the domestic counter terrorism system of aviation so as to preemptively respond to the international terrorism. This study propose the following measures to improve the aviation security system by (1) create 'Aviation Special Judicial Police' (2) revise the anti-terrorism law and aviation security law (3) Strengthening the ability respond to terrorism in cyberspace (4) building an international cooperation network for aviation terrorism.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.6
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• pp.63-69
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• 2008

Reconfigurable RF one-chip solutions have been researched with the objective of designing for smaller-sized and more economical RF transceiver and it can be applied to a vehicular wireless terminal. The proposed voltage-controlled oscillator satisfies the targeted frequency range ($4.2{\sim}5.4\;GHz$) and the frequency planning which correspond to the standards such as CDMA(IS-95), PCS, GSM850, EGSM, WCDMA, WLAN, Bluetooth, WiBro, S-DMB, DSRC, GPS, and DVB-H/DMB-H/L(L Band). In order to improve phase noise performance, PMOS is adopted in the cross-coupled pair, the tail current source and MOS varactor in this VCO and differential-typed switching is proposed in capacitor array. Based on the measurement results, a total power dissipation is $5.3{\sim}6.0\;mW$ at 1.8 V power supply voltage. The oscillator is tuned from 4.05 to 5.62 GHz; The tuning range is 33%. The phase noise is -117.16 dBc/Hz at 1 MHz offset frequency and the FOM (Figure Of Merit) is $-180.84{\sim}-180.5$.

• Asian-Australasian Journal of Animal Sciences
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• v.31 no.6
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• pp.784-790
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• 2018

Objective: The genetic effects of an individual on the phenotypes of its social partners, such as its pen mates, are known as social genetic effects. This study aims to identify the candidate genes for social (pen-mates') average daily gain (ADG) in pigs by using the genome-wide association approach. Methods: Social ADG (sADG) was the average ADG of unrelated pen-mates (strangers). We used the phenotype data (16,802 records) after correcting for batch (week), sex, pen, number of strangers (1 to 7 pigs) in the pen, full-sib rate (0% to 80%) within pen, and age at the end of the test. A total of 1,041 pigs from Landrace breeds were genotyped using the Illumina PorcineSNP60 v2 BeadChip panel, which comprised 61,565 single nucleotide polymorphism (SNP) markers. After quality control, 909 individuals and 39,837 markers remained for sADG in genome-wide association study. Results: We detected five new SNPs, all on chromosome 6, which have not been associated with social ADG or other growth traits to date. One SNP was inside the prostaglandin $F2{\alpha}$ receptor (PTGFR) gene, another SNP was located 22 kb upstream of gene interferon-induced protein 44 (IFI44), and the last three SNPs were between 161 kb and 191 kb upstream of the EGF latrophilin and seven transmembrane domain-containing protein 1 (ELTD1) gene. PTGFR, IFI44, and ELTD1 were never associated with social interaction and social genetic effects in any of the previous studies. Conclusion: The identification of several genomic regions, and candidate genes associated with social genetic effects reported here, could contribute to a better understanding of the genetic basis of interaction traits for ADG. In conclusion, we suggest that the PTGFR, IFI44, and ELTD1 may be used as a molecular marker for sADG, although their functional effect was not defined yet. Thus, it will be of interest to execute association studies in those genes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.101-108
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• 2007

In this paper, we propose and verify an adaptive block watermarking algorithm based on JPEG2000 DWT, which determines watermarking for the original image by two scaling factors in order to overcome image degradation and blocking problem at the edge. Adaptive block watermarking algorithm uses 2 scaling factors, one is calculated by the ratio of present block average to the next block average, and the other is calculated by the ratio of total LL subband average to each block average. Signals of adaptive block watermark are obtained from an original image by itself and the strength of watermark is automatically controlled by image characters. Instead of conventional methods using identical intensity of a watermark, the proposed method uses adaptive watermark with different intensity controlled by each block. Thus, an adaptive block watermark improves the visuality of images by 4$\sim$14dB and it is robust against attacks such as filtering, JPEG2000 compression, resizing and cropping. Also we implemented the algorithm in ASIC using Hynix 0.25${\mu}m$ CMOS technology to integrate it in JPEG2000 codec chip.

• The Journal of the Korea Contents Association
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• v.20 no.6
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• pp.99-113
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• 2020

In the future, robots and drones for the convenience of our lives in everyday life will increase. As a method for controlling this, a remote control or a human voice method is most commonly used. However, the remote control needs to be operated by a person and can not ignore ambient noise in the case of voice. In this paper, we propose an economical attitude information acquisition method to accurately acquire the posture information of the arm in real time under the assumption that the surround drones or robots can be controlled wirelessly with the posture information of the arm. For this purpose, the extended Kalman filter was used to eliminate the noise of the arm position information. in order to detect the arm movement, a low cost MEMS type sensor was applied to secure the economical efficiency of the apparatus. To increase the wear ability of the arm, We developed a compact and lightweight attitude information acquisition system by integrating all functions into one chip as much as possible. As a result, the real-time performance of 1 ms was secured and the extended Kalman filter was applied to acquire the accurate attitude information of the arm with noise removed and display the attitude information of the arm in real time. This provides a basis for generating commands using real-time attitude information of the arm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.5
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• pp.307-312
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• 2018

Liquid phases in ZnO varistors cause more complex phase development and microstructure, which makes the control of electrical properties and reliability more difficult. Therefore, we have investigated 2 mol% $CaCO_3$ doped $ZnO-Co_3O_4-Cr_2O_3-La_2O_3$ (ZCCLCa) bulk ceramics as one of the compositions without liquid phase sintering additive. The results were as follows: when $CaCO_3$ is added to ZCCLCa ($644{\Omega}cm$) acting as a simple ohmic resistor, CaO does not form a secondary phase with ZnO but is mostly distributed in the grain boundary and has excellent varistor characteristics (high nonlinear coefficient ${\alpha}=78$, low leakage current of $0.06{\mu}A/cm^2$, and high insulation resistance of $1{\times}10^{11}{\Omega}cm$). The main defects $Zn_i^{{\cdot}{\cdot}}$ (AS: 0.16 eV, IS & MS: 0.20 eV) and $V_o^{\bullet}$ (AS: 0.29 eV, IS & MS: 0.37 eV) were found, and the grain boundaries had 1.1 eV with electrically single grain boundary. The resistance of each defect and grain boundary decreases exponentially with increasing the measurement temperature. However, the capacitance (0.2 nF) of the grain boundary was ~1/10 lower than that of the two defects (~3.8 nF, ~2.2 nF) and showed a tendency to decrease as the measurement temperature increased. Therefore, ZCCLCa varistors have high sintering temperature of $1,200^{\circ}C$ due to lack of liquid phase additives, but excellent varistor characteristics are exhibited, which means ZCCLCa is a good candidate for realizing chip type or disc type commercial varistor products with excellent performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.32-40
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• 2016

IEEE 802.15.4 is the one of the protocols for radio communication in a personal area network. Because of low cost and low power communication for IoT communication, it requires the highest optimization level in the implementation. Recently, the studies of location aware algorithm based on IEEE802.15.4 standard has been achieved. Location estimation is performed basically in equal consideration of reference node information and blind node information. However, an error is not calculated in this algorithm despite the fact that the coordinates of the estimated location of the blind node include an error. In this paper, we enhanced a conventual maximum likelihood estimation using weighted coefficient and implement the hardwired location aware engine for small code size and low power consumption. On the field test using test-beds, the suggested hardware based location awareness method results better accuracy by 10 percents and reduces both calculation and memory access by 30 percents, which improves the systems power consumption.