• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• 2004.11a
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• pp.250-255
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• 2004

To analyze delay, Seoul - Daegu line of Korea High Speed Railway was divided into three sections and analyzed independently by the business characteristics. The analysis on the project delay reasons was performed on macro and micro scales. This analytic method was named as 'Macro-Micro Delay Analysis Method (MMDAM)'. The macro scale analysis has three approaches, which are (1) scheduling, (3) structural characteristic, (3) and responsibility of project administrative works. Micro analysis also has three, methodologies which are (1) As Planned Method, (2) As Built method, (3) Modified Time Impact Analysis for analyzing the most influential section which the largest delay occurred. Using elicited project delay reasons from above analysis, the questionnaire was carried out for analyzing the influence of project delay reason. The reasons of the delay were driven from two different aspects (1) structural characteristic and (2) responsibility of the people involved in the project. The reasons that were identified from aforementioned three sections are the factors of the delay of the large-scale government driven projects. Finally, the author suggested the methodology of identifying the project delaying factors. The author also analyzed delay reasons in both the overseas and domestic cases of high rapid railway construction and has elicited some benchmarks for the future projects.