• Title/Summary/Keyword: On-Board Computer

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Design and Implementation of Software Program based on Web for Basic Electronic Circuit Practice (기초전기전자회로 실습을 위한 웹 기반 소프트웨어 프로그램의 설계 및 구현)

  • Lee, Young-joo;Hwang, Joon-won;Hwang, Dae-min;Yun, Kyung-min;Lee, Bo-Gon;Yu, Seon-Tae;Moon, Il-Young
    • Journal of Practical Engineering Education
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    • v.7 no.2
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    • pp.113-117
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    • 2015
  • In this academic paper, we introduce a bread board simulation which is developed based on HTML language. this program is developed because actual electronic practices have some problems. Electronic circuit practice using bread board is widely practiced in colleges or high schools in South Korea, but actual electronic circuit practice needs lots of consumable stuff, and they are needed to be purchased and managed continuously. Besides, composing complicated electronic circuit restricts the efficiency of studying. Therefore, we propose breadboard simulation program which helps to resolve those problems.

DESIGN AND IMPLEMENTATION OF THE SMALL SATELLITE ON-BOARD COMPUTER SYSTEM : KASCOM (소형위성의 제어를 위한 컴퓨터 시스템의 설계 및 구현)

  • 김기형;김형신;박재현;박규호;최순달
    • Journal of Astronomy and Space Sciences
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    • v.13 no.2
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    • pp.52-66
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    • 1996
  • In this paper, we present the design methodology of KASCOM(KAIST satellite computer), the experimental on-board computer system of KITSAT-2. The design of the on-board computer system should consider the following constraints: operational throughput, fault tolerant input-output, low power, size, weight, and radiation hardness. KASCOM is designed to satisfy these constraints. This paper also presents the implementation and testing details of KASCOM. Finally, the in-orbit operational results are presented. The results show that about 2 SEU errors occur for the program memory(1Mbit SRAM) in a day, while 3.7 SEU errors occur for the data memory(4Mbit SRAM). This implies that high-integrated memories are more susceptible to the radiation environment than low-integrated memories.

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Design and Fabrication of Printed Circuit Board (PCB) Integrated Energy Harvester (PCB 일체형 에너지 하베스터의 설계 및 제작)

  • Min, Chul Hong;Kim, Tae Seon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.11
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    • pp.846-851
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    • 2013
  • Recently, energy harvesting technologies are considered as the great alternatives to reduce the dependency on secondary batteries. In this paper, we proposed PCB type energy harvester which can be directly integrated with other electronic components on same board. To form the three dimensional coil structure, two PCBs with patterned metal lines are solder bonded. For magnetic induction, inside of coil structure was filled with magnetic substance and rotary motioned external magnets are applied to near the harvester. The effects of metal wire width on PCB, thickness of magnetic substance, and frequency of rotary motion on energy harvesting performance are analyzed by computer simulation and experiments. Experimental results showed 29.89 ${\mu}W$ of power generation performance at the frequency of 5.2 Hz and it is shown that designed harvester can be effectively applied on vibration environment with very limited frequency.

The development of Fetal Heart Rate monitoring system based on DSP processor (DSP 프로세서를 이용한 태아심음 및 자궁수축감시장치의 개발)

  • Jnag, D.P.;Kim, K.H.;Lee, Y.H.;Lee, Y.K.;Bak, M.I.;Lee, D.S.;Kim, S.I.
    • Proceedings of the KOSOMBE Conference
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    • v.1996 no.05
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    • pp.320-324
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    • 1996
  • Digital fetal monitoring system based on the personal computer combined with the digital signal processing board was implemented. The DSP board acquires and digitally processes ultrasound fetal Doppler signal for digital rectification, FIR filtering, autocorrelation function calculation, its peak detection and MEDIAN filtering. The personal computer interfaced with the DSP board is in charge of graphic display, hardcopy, data transmission and on-line analysis of fetal heart rate change including and variability. I used a recursive technique for autocorrelation function computation method and MEDIAN filter which can greatly reduce the amount of calculation and accuracy. I also implemented analysis algorithm of fetal heart rate change based on normal fetal sample data in order to exact diagnosis.

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Design and Implementation of a Processor Monitor and Fault Injection System for Next Generation Spacecraft Computer Board (차세대 위성탑재컴퓨터를 위한 프로세서 모니터 및 고장주입 시스템의 설계 및 구현)

  • Jeong, Jae-Yeop;Choi, Jong-Wook;Cheon, Yee-Jin
    • Journal of Satellite, Information and Communications
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    • v.9 no.4
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    • pp.97-103
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    • 2014
  • In order to verify normal operation of satellite OBC(On Board Computer), it is essential that processor monitoring and debugging. So we are using the GRMON of Aeroflex Gaisler. It provides a lot of features for debugging of LEON processor but we can't use that features on the NGSCB(Next Generation Spacecraft Computer Board) except a few things. So the cost-effectiveness is very low. And for hardware fault injection, we are using a method of modify satellite flight software, because we can't modify GRMON. This method can not guarantee normal operation of the satellite flight software. So in this paper we were developed the processor monitoring and fault injection tool for NGSCB.

Implementation of Main Computation Board for Safety Improvement of railway system (철도시스템의 안전성 향상을 위한 주연산보드 구현)

  • Park, Joo-Yul;Kim, Hyo-Sang;Lee, Joon-Hwan;Kim, Bong-Taek;Chung, Ki-Seok
    • Proceedings of the KSR Conference
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    • 2011.05a
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    • pp.1195-1201
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    • 2011
  • Since the release of safety standard IEC 61508 which defines functional safety of electronic safety-related systems, SIL(Safety Integrity Level) certification for railway systems has gained lots of attention lately. In this paper, we propose a new design technique of the computer board for train control systems with high reliability and safety. The board is designed with TMR(Triple Modular Redundancy) using a certified SIL3 Texas Instrument(TI)'s TMS570 MCU(Micro-Controller Unit) to guarantee safety and reliability. TMR for the control device is implemented on FPGA(Field Programmable Gate Array) which integrates a comparator, a CAN(Controller Area Network) communication module, built-in self-error checking, error discriminant function to improve the reliability of the board. Even if a malfunction of a processing module occurs, the safety control function based on the proposed technique lets the system operate properly by detecting and masking the malfunction. An RTOS (Real Time Operation System) called FreeRTOS is ported on the board so that reliable and stable operation and convenient software development can be provided.

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Learning System for Big Data Analysis based on the Raspberry Pi Board (라즈베리파이 보드 기반의 빅데이터 분석을 위한 학습 시스템)

  • Kim, Young-Geun;Jo, Min-Hui;Kim, Won-Jung
    • The Journal of the Korea institute of electronic communication sciences
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    • v.11 no.4
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    • pp.433-440
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    • 2016
  • In order to construct a system for big data processing, one needs to configure the node by using network equipments to connect multiple computers or establish cloud environments through virtual hosts on a single computer. However, there are many restrictions on constructing the big data analysis system including complex system configuration and cost. These constraints are becoming a major obstacle to professional manpower training for big data areas which is emerging as one of the most important national competitiveness. As a result, for professional manpower training of big data areas, this paper proposes a Raspberry Pi Board based educational big data processing system which is capable of practical training at an affordable price.

ESTIMATION OF SEU THRESHOLD ENERGY FROM KITSAT-1 DATA USING AP-8 MODEL (AP-8 모델을 이용한 우리별 1호 SEU 문턱에너지 추정)

  • 김성준;신영훈;김성수;민경욱
    • Journal of Astronomy and Space Sciences
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    • v.18 no.2
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    • pp.109-118
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    • 2001
  • KITSAT-1, launched in 1992, passes through Inner Van Allen Radiation Belt in which high energy Protons cause single event upsets(SBUs) in the main memory of KITSAT-1 OBC(On-Board Computer) 186. The present paper compares SEU data from the OBC186 with the AP-8 model of NASA/NSSDC using the Chi-Square method to estimate the SEU threshold energy. Shielding effect by the satellite body has been taken into account to model the proton fluxes at the position of OBC186, and SEUs recorded during the high solar activities have been removed to avoid the spurious result. The result shows that the SEU threshold energy of the main memory of KITSAT-1 OBC186 is estimated to be about $110{pm}10MeV$.

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Structural Improvement for Crack of Integrated Circuit in Single Board Computer by Structure Analysis (단일보드컴퓨터 구조해석을 통한 집적회로 균열현상의 구조적 개선)

  • Ryu, Jeong-min;Lee, Yong-jun;Sohn, Kwonil
    • Journal of Advanced Navigation Technology
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    • v.23 no.5
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    • pp.460-465
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    • 2019
  • In this study, we aim to derive a solution from the structural analysis for electrical failure of single board computers for computing navigation information. By analyzing the characteristic factor, we identify that crack occur on the central processing unit board due to a certain structural problem, and that the physical effect by the crack make communication function be impossible to perform, which it causes booting error. In order to find the location of excessive stress causing the crack, structural analysis for the single board computer is done. From the structural analysis, the areas where stress concentration occurs are identified, and improvement methods changing the structures are developed. As a result, we shows that stresses are reduced entirely on the stress distribution for the improved structure. In addition, heat analysis shows that changing the structure to reduce stresses is not affect to the heat radiation, and the thermal resistance of the actual equipment is verified by measuring the temperature of the heat sink applied with the improved structure.

A Development of Real-time Monitoring Techniques for Synchronous Electric Generator Systems (동기 발전기 시스템의 실시간 모니터링 기술 개발)

  • Cho, Hyun Cheol
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.66 no.4
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    • pp.182-187
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    • 2017
  • Synchronous generators have been significantly applied in large-scale power plants and its monitoring systems are additionally established to sequentially observe states and outputs. We develop a computer based monitoring device for three-phase synchronous power generators in this paper. First, a test-bed of such generator system is created and then a interface board is constructed to transfer electric signals including the output voltage and the current from generators into a computer system via a data acquisition device. Its RMS(root-mean-square) values are continuously shown on a screen of computer systems and its time-histories graphs are additionally illustrated under a graphic user interface(GUI) mode. Lastly, we carry out real-time experiments using the generator system with the monitoring device to demonstrate its reliability and superiority by comparing results of a generic power analyzer which is well-used in measuring various power systems practically.