• 전기학회논문지
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• 제58권2호
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• pp.285-291
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• 2009

In this paper, comparative analysis of offset voltage PWM method and $V_{max}-V_{mid}$ PWM method for three-phase matrix converter is addressed by using a simple analytical and graphical method. Offset voltage PWM method calculates PWM patterns in terms of offset voltage and variable slope of carrier, and it simplifies matrix converter modulation algorithm significantly. $V_{max}-V_{mid}$ PWM method generates patterns by using two phases and maintaining a remaining phase to base phase, and it is implemented in the industrial products. The most important performance criterion of modulation method is a magnitude of current ripples and it is analytically modelled. The graphical illustration of theses complex multivariable functions make per-carrier cycle and per fundamental cycle behavior of two PWM methods understood. Two modulation methods are analysed with the analytical formulas and graphics, and the analysis shows offset voltage PWM method is superior to $V_{max}-V_{mid}$ PWM method with respect to input current ripples and output voltage ripples.

• Journal of Power Electronics
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• 제15권2호
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• pp.504-517
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• 2015

This paper presents a novel switching voltage model and an offset-based pulse width modulation (PWM) scheme for multilevel inverters with unbalanced DC sources. The switching voltage model under a DC voltage imbalance will be formulated in general form for multilevel neutral-point-clamped topologies. Analysis of the reference switching voltages from active and non-active switching voltage components in abc coordinates can enable voltage implementation for an unbalanced DC-source condition. Offset voltage is introduced as an indispensable variable in the switching voltage model for multilevel voltage-source inverters. The PWM performance is controlled through the design of two offset components in a subsequence. One main offset may refer to the common mode voltage, and the other offset restricts its effect on the quality of PWM control in related DC levels. The PWM quality can be improved as the switching loss is reduced in a discontinuous PWM mode by setting the local offset, which is related to the load currents. The validity of the proposed algorithm is verified by experimental results.

• 전기전자학회논문지
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• 제23권4호
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• pp.1140-1149
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• 2019

전압형 컨버터의 다양한 전압 합성 방법을 구현하기 위해서, 옵셋 전압을 주입하는 방법이 널리 사용되고 있다. 즉, 전압 변조 방식(pulse width modulation; PWM)들은 교류 측 전압 지령에 적절한 옵셋 전압을 주입하는 것과 수학적으로 동일하다. 이러한 옵셋 전압을 이용한 AC 단 출력 전압 합성 방법에 따라 DC 단 전압의 전압 이용률이 달라지며, 이는 모듈형 다단 컨버터(modular multilevel converter; MMC) 시스템에서도 동일하다. 따라서, DC 단의 용량이 정해져 있는 고압 직류(high voltage DC; HVDC) 송전 시스템의 경우에도 AC 단에 옵셋 전압을 이용함에 따라 AC 단으로 공급 가능한 최대 무효 전력의 크기를 변화시킬 수 있다. 본 논문에서는 대표적인 전압 변조 방식을 적용한 옵셋 전압 주입 시 합성된 AC 측 출력 전압에 따라 MMC 시스템의 레그 에너지 맥동을 수학적으로 분석하였다. 또한, 이를 실제 스케일의 400MVA급 MMC 시스템 시뮬레이션을 통해 수학적 분석의 경향성을 검증하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 추계학술대회
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• pp.221-222
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• 2011

본 논문은 인버터의 PWM구동 시 출력 전류에 발생하는 DC offset을 제거 하는 방법을 제안한다. 인버터의 PWM구동 시 소자 단락을 막기 위해 필수적으로 적용하는 deadtime과 각 스위치 소자의 voltage drop으로 인해 출력에 왜곡이 발생한다. 이상적인 스위치인 경우에는 이 두 가지의 왜곡을 feedforward로 보상하면 된다. 하지만 스위치 소자가 이상적이지 않기 때문에 각 스위치 소자의 voltage drop의 차이와 on & off time delay의 차이는 출력 전류에 DC offset을 발생시킨다. 따라서 deadtime과 스위치 voltage drop에 대한 보상과 함께 출력 전류의 DC offset을 feedback으로 하여 보상되지 못한 왜곡을 추가적으로 보상하여 결론적으로 출력 전류의 DC offset을 제거할 수 있게 하였다. 제안된 기법은 시뮬레이션을 통하여 그 타당성을 확인하였다.

• 전력전자학회논문지
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• 제22권1호
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• pp.67-74
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• 2017

This study proposes a novel random pulse-width modulation (PWM) technique with a constant switching frequency utilizing a random offset voltage. The proposed PWM technique spreads switching harmonics by varying the position of an active voltage vector without a switching frequency variation. The implementation of the proposed PWM technique is simple because it does not require additional hardware and complex algorithm. The proposed random PWM technique is compared with the conventional PWM technique on the factors of harmonic spectrum, total harmonic distortion, and harmonic spread factor to confirm the harmonic spread effect. The validity of the proposed method is verified by simulations and experiments on a three-phase inverter drive system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 B
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• pp.1088-1090
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• 2004

This paper presents control pattern of air-cored slotless permanent magnet linear synchronous motor using voltage modulation method which is used space vector voltage modulation and offset voltage modulation.

• 전력전자학회논문지
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• 제25권1호
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• pp.68-71
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• 2020

As a T-type three-level PWM converter has several intrinsic advantages, it has been widely studied for many applications. However, it requires an additional voltage control loop for balancing each DC link voltage. Generally, satisfying this requirement involves the use of an offset voltage to provide a neutral point current without affecting other variables, such as the total DC link voltage and three-phase input current. In this study, the theoretical relationship between the offset voltage and the neutral point current is analyzed. The results can be beneficial for effective voltage balancing controller design. The effectiveness of the analytical modeling is verified by simulation and experimental results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.498-499
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• 2014

본 논문에서는 3상 PWM 옵셋전압방식을 응용하여 2상 인버터에 대한 PWM 제어방식을 확립하였다. 또한 기존의 3상 PWM 인버터 옵셋전압방식과의 최대 전압영역과 비교 분석하였다.

• Journal of Power Electronics
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• 제12권4호
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• pp.548-558
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• 2012

In this paper, a novel offset-based single-state pulse width modulation (PWM) method for achieving zero common-mode voltage (CMV) and reducing switching losses in multilevel inverters is presented. The specific active switching state of the zero common-mode (ZCM) voltage that approximates the reference voltage can be deduced from the switching state sequence of the reduced CMV phase disposition PWM (CMV PD PWM) method. From the reference leg voltages for the zero common-mode voltage, an N-to-2-level transformation defines a virtual two-level inverter and the corresponding nominal leg voltage references. The commutation process of the reduced CMV PD PWM method in a multilevel inverter and its outputs can be simply followed in a nominal switching time diagram for the virtual inverter. The characteristics of the reduced CMV PD PWM and the single-state PWM for zero common-mode voltage are analyzed in detail in this paper. The theoretical analysis of the proposed PWM method is verified by experimental results.

• 전력전자학회논문지
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• 제19권6호
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• pp.488-493
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• 2014

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.