• Title/Summary/Keyword: Odd number of Folding Block

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An 1.2V 8-bit 800MSPS CMOS A/D Converter with an Odd Number of Folding Block (홀수개의 폴딩 블록으로 구현된 1.2V 8-bit 800MSPS CMOS A/D 변환기)

  • Lee, Dong-Heon;Moon, Jun-Ho;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.7
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    • pp.61-69
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    • 2010
  • In this paper, an 1.2V 8b 800MSPS A/D Converter(ADC) with an odd number of folding block to overcome the asymmetrical boundary-condition error is described. The architecture of the proposed ADC is based on a cascaded folding architecture using resistive interpolation technique for low power consumption and high input frequency. The ADC employs a novel odd folding block to improve the distortion of signal linearity and to reduce the offset errors. In the digital block, furthermore, we use a ROM encoder to convert a none-$2^n$-period code into the binary code. The chip has been fabricated with an $0.13{\mu}m$ 1P6M CMOS technology. The effective chip area is $870{\mu}m\times980{\mu}m$. SNDR is 44.84dB (ENOB 7.15bit) and SFDR is 52.17dBc, when the input frequency is 10MHz at sampling frequency of 800MHz.