• 한국전기전자재료학회논문지
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• 제13권11호
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• pp.914-920
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• 2000

When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

• 한국재료학회지
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• 제1권4호
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• pp.229-235
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• 1991

$Ta_2O_5$ 박막은 실리콘산화막, 실리콘질화막 박막에 비해 유전율은 높으나 누설전류밀도가 높고, 절연파괴강도가 낮아 DRAM의 커패시터용 재료로서 실용화가 되지 못하고 있다. 본 연구에서는 LPCVD법으로 형성시킨 $300{\AA}$ 두께의 $Ta_2O_5$ 유전체박막에 대해 후속열처리 또는 전극재료를 변화시켜 열악한 전기적 특성의 원인을 규명하고자 하였다. 그 결과 다결정 실리콘 전극의 경우 성막상태의 $Ta_2O_5$ 박막은 전극에 의한 환원반응에 의해 전기적 특성이 열화됨을 알 수 있었고, 이를 TiN 전극의 사용으로 억제시킬 수 있었다. 다결정 실리콘 전극의 경우 성막상태의 $Ta_2O_5$ 유전체는 누설정류밀도가 $10^{-1}A/cm^2$, 절연파괴강도가 1.5MV/cm 정도였으며, $800^{\circ}C$에서 $O_2$열처리를 하면 전기적 특성은 개선되나, 유전율이 낮아진다 TiN 전극을 채용할 경우 누설전류밀도 $10^{-6}~10^{-7}A/cm^2$, 절연파괴강도 7~12MV/cm 로 ONO(Oxide-Nitride-Oxide) 박막과 비슷한 $Ta_2O_5$ 고유전막을 얻을 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권4호
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.