• Title/Summary/Keyword: O-Algorithm

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File System Support for Multimedia Streaming in Internet Home Appliances (인터넷 홈서버를 위한 스트리밍 전용 파일 시스템)

  • 박진연;송승호;진종현;원유집;박승민;김정기
    • Journal of Broadcast Engineering
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    • v.6 no.3
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    • pp.246-259
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    • 2001
  • Due to recent rapid deployment of Internet streaming service and digital broadcasting service, the issue of how to efficiently support streaming workload in so called "Internet Home Appliance" receives prime interests from industry as well as academia. The underlying dilemma is that it may not be feasible to put cutting edge CPU, boards, disks and other peripherals into that type of device. The primary reason is its cost. Usually, Internet Home Appliances has its dedicated usage, e.g. Internet Radio, and thus it does not require high-end CPU nor high-end Va subsystem. The same reasoning applies to I/O subsystem. In Internet Home Appliances dedicated to handle compressed moving picture, it is not equipped with high end SCSI disk with fast rotational speed. Thus, it is mandatory to devise elaborate software algorithm to exploit the available hardware resources and maximize the efficiency of the system. This paper presents our experiences in the design and implementation of a new multimedia file system which can efficiently deliver the required disk bandwidth for a periodic I/O workload. We have implemented the file system on the Linux operating system, and examined itsperformance under streaming I/O workload. The results of the study show that the proposed file system exhibits superior performance than the Linux Ext2 file system under streaming I/O workload. The result of this work not only contribute to advance the state f art file system technology for multimedia streaming but also put forth the software which is readily available and can be deployed. deployed.

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Performance Evaluation of Hash Join Algorithm on Flash Memory SSDs (플래쉬 메모리 SSD 기반 해쉬 조인 알고리즘의 성능 평가)

  • Park, Jang-Woo;Park, Sang-Shin;Lee, Sang-Won;Park, Chan-Ik
    • Journal of KIISE:Computing Practices and Letters
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    • v.16 no.11
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    • pp.1031-1040
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    • 2010
  • Hash join is one of the core algorithms in databases management systems. If a hash join cannot complete in one-pass because the available memory is insufficient (i.e., hash table overflow), however, it may incur a few sequential writes and excessive random reads. With harddisk as the tempoary storage for hash joins, the I/O time would be dominated by slow random reads in its probing phase. Meanwhile, flash memory based SSDs (flash SSDs) are becoming popular, and we will witness in the foreseeable future that flash SSDs replace harddisks in enterprise databases. In contrast to harddisk, flash SSD without any mechanical component has fast latency in random reads, and thus it can boost hash join performance. In this paper, we investigate several important and practical issues when flash SSD is used as tempoary storage for hash join. First, we reveal the va patterns of hash join in detail and explain why flash SSD can outperform harddisk by more than an order of magnitude. Second, we present and analyze the impact of cluster size (i.e., va unit in hash join) on performance. Finally, we emperically demonstrate that, while a commerical query optimizer is error-prone in predicting the execution time with harddisk as temporary storage, it can precisely estimate the execution time with flash SSD. In summary, we show that, when used as temporary storage for hash join, flash SSD will provide more reliable cost estimation as well as fast performance.

A study on bio-signal process for prosthesis arm control (인공의수의 능동 제어를 위한 생체 신호 처리에 관한 연구)

  • Ahn, Young-Myung;Yoo, Jae-Myung
    • 전자공학회논문지 IE
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    • v.43 no.4
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    • pp.28-36
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    • 2006
  • In this paper, an algorithm to classify the 4 motions of arm and a control system to position control the prosthesis are studied. To classify the 4 motions, we use flex sensors which is electrical resistance type sensor that can measure warp of muscle. The flex sensors are attached to the biceps brchii muscle and coracobrachialis muscle and the sensor signals are passed the sensing system. 4 motion of the forearm - flexion and extension, the pronation and supination are classified from this. Also position of forearm is measured from the classified signals. Finally, A two D.O.F prosthesis arm with RC servo-motor is designed to verify the validity of the algorithm. At this time, fuzzy controller is used to reduce the position error by rotary inertia and noise. From the experiment, the position error had occurred within about 5 degree.

Fast Micro-mobility Management Scheme without DAD Session in HMIPv6 Networks (계층적 Mobile IPv6 기반의 빠른 Micromobility 관리 프로토콜)

  • Lee, Sung-Kuen;Kim, Eal-Lae;Lim, Tae-Hyung;Jeong, Seok-Jong;Park, Jin-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.7A
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    • pp.746-754
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    • 2007
  • In this paper, we propose a fast handoff algorithm for micromobility management enhancement in HMIPv6 networks, which eliminates the DAD procedure involved in the regular HMIPv6 in order to o decrease handoff latency and increase the resource utilization efficiency. In the proposed scheme, the MAP is designed to guarantee the uniqueness of MN's interface identifier within a MAP domain as long as the MN moves in a MAP domain, so that the MN configures the new address without the DAD procedure resulting in the decreased handoff latency significantly When the MN resides in a subnet, MIPv6 is used adaptively as a mobility management protocol, which is to reduce bandwidth waste from the IP packet header overhead of IP-in-IP tunneling from the regular HMIPv6. We evaluate the performance of the proposed handoff micromobility algorithm in terms of handoff delay and packet loss thru computer simulation. Thru various computer simulation results, we verified the superior performance of the proposed scheme by comparing with the results of other schemes, MIPv6 and HMIPv6.

Error Recovery Schemes with IPv6 Header Compression (IPv6 헤더 압축에서의 에러 복구방안)

  • Ha Joon-Soo;Choi Hyun-Jun;Seo Young-Ho;Kim Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.7
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    • pp.1237-1245
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    • 2006
  • This paper presented a hardware implementation of ARIA, which is a Korean standard l28-bit block cryptography algorithm. In this work, ARIA was designed technology-independently for application such as ASIC or core-based designs. ARIA algorithm was fitted in FPGA without additional components of hardware or software. It was confirmed that the rate of resource usage is about 19% in Altera EPXAl0F1020CI and the resulting design operates stably in a clock frequency of 36.35MHz, whose encryption/decryption rate was 310.3Mbps. Consequently, the proposed hardware implementation of ARIA is expected to have a lot of application fields which need high speed process such as electronic commerce, mobile communication, network security and the fields requiring lots of data storing where many users need processing large amount of data simultaneously.

A Density-based k-Nearest Neighbors Query Method (밀도 기반의 k-최근접 질의 처리)

  • Jang, In-Sung;Han, Eun-Young;Cho, Dae-Soo
    • Journal of the Korean Association of Geographic Information Studies
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    • v.6 no.4
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    • pp.59-70
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    • 2003
  • Spatial data base system provides many query types and most of them are required frequent disk I/O and much CPU time. k-NN search is to find k-th closest object from the query point and up to now, several k-NN search methods have been proposed. Among these, MINMAX distance method has an aim not to access unnecessary node by adapting pruning technique. But this method accesses more disks than necessary while pruning unnecessary nodes. In this paper, we propose new k-NN search algorithm based on density of object. With this method, we predict the radius to be expected to contain k-NN objects using density of data set and search those objects within this radius and then adjust radius if failed. Experimental results show that this method outperforms the previous MINMAX distance method. This algorithm visit less disks than MINMAX method by the factor of maximum 22% and average 7%.

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A SOC Design Methodology using SystemC (SystemC를 이용한 SOC 설계 방법)

  • 홍진석;김주선;배점한
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.153-156
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    • 2000
  • This paper presents a SOC design methodology using the newly-emerging SystemC. The suggested methodology firstly uses SystemC to define blocks from the previously-developed system level algorithm with internal behavior and interface being separated and validate such a described blocks' functionality when integrated. Next, the partitioning between software and hardware is considered. With software, the interface to hardware is described cycle-accurate and the other internal behavior in conventional ways. With hardware, I/O transactions are refined gradually in several abstraction levels and internal behavior described on a function basis. Once hardware and software have been completed functionally, system performance analysis is performed on the built model with assumed performance factors and influences such decisions regressively as on optimum algorithm selection, partitioning and etc. The analysis then gives constraint information when hardware description undergoes scheduling and fixed-point trans- formation with the help of automatic translation tools or manually. The methodology enables C/C++ program developers and VHDL/Verilog users to migrate quickly to a co-design & co-verification environment and is suitable for SoC development at a low cost.

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VLSI Design for Motion Estimation Based on Bit-plane Matching (비트 플레인 정합에 의한 움직임 추정기의 VLSI 설계)

  • Go, Yeong-Gi;O, Hyeong-Cheol;Go, Seong-Je
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.5
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    • pp.509-517
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    • 2001
  • Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

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EZXover: C program to Reduce Cross-over Errors in Marine Geophysical Survey Data (지구물리탐사자료에서 교차점오차를 보정하기위한 EZXover 프로그램 개발)

  • Kang Moo-Hee;Han Hyun-Chul;Kim Kyong-O;SunWoo Don;Kim Jin-Ho;Gong Gee-Soo
    • Economic and Environmental Geology
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    • v.39 no.3 s.178
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    • pp.229-234
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    • 2006
  • Cross-over errors (XOEs) may mislead scientists when interpreting marine geophysical data. Such risk can be reduced by correcting the data proportionally between two cross-over points (XOPs). C program is presented to determine XOPs using a quick rejection test and a straddle test, and to adjust XOEs using a weighted linear interpolation algorithm.

Material Optimization of BIW for Minimizing Weight (경량화를 위한 BIW 소재 최적설계)

  • Jin, Sungwan;Park, Dohyun;Lee, Gabseong;Kim, Chang Won;Yang, Heui Won;Kim, Dae Seung;Choi, Dong-Hoon
    • Transactions of the Korean Society of Automotive Engineers
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    • v.21 no.4
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    • pp.16-22
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    • 2013
  • In this study, we propose the method of optimally changing material of BIW for minimizing weight while satisfying vehicle requirements on static stiffness. First, we formulate a material selection optimization problem. Next, we establish the CAE procedure of evaluating static stiffness. Then, to enhance the efficiency of design work, we integrate and automate the established CAE procedure using a commercial process integration and design optimization (PIDO) tool, PIAnO. For effective optimization, we adopt the approach of metamodel based approximate optimization. As a sampling method, an orthogonal array (OA) is used for selecting sampling points. The response values are evaluated at the sampling points and then these response values are used to generate a metamodel of each response using the linear polynomial regression (PR) model. Using the linear PR model, optimization is carried out an evolutionary algorithm (EA) that can handle discrete design variables. Material optimization result reveals that the weight is reduced by 44.8% while satisfying all the design constraints.