• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 하계학술대회 논문집
• /
• pp.305-309
• /
• 2002

We have successfully fabricated a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure using Bi$\sub$4-x/La$\sub$x/Ti$_3$O$\sub$12/ (BLT) ferroelectric thin film and SiO$_2$/Nitride/SiO$_2$ (ONO) stacked buffer layers for single transistor type ferroelectric nonvolatile memory applications. BLT films were deposited on 15 nm-thick ONO buffer layer by sol-gel spin-coating. The dielectric constant and the leakage current density of prepared ONO film were measured to be 5.6 and 1.0 x 10$\^$-8/ A/$\textrm{cm}^2$ at 2MV/cm, respectively, It was interesting to note that the crystallographic orientations of BLT thin films were strongly effected by pre-bake temperatures. X-ray diffraction patterns showed that (117) crystallites were mainly detected in the BLT film if pre-baked below 400$^{\circ}C$. Whereas, for the films pre-baked above 500$^{\circ}C$, the crystallites with preferred c-axis orientation were mainly detected. From the C-V measurement of the MFIS capacitor with c-axis oriented BLT films, the memory window of 0.6 V was obtained at a voltage sweep of ${\pm}$8 V, which evidently reflects the ferroelectric memory effect of a BLT/ONO/Si structure.

• 한국표면공학회지
• /
• 제55권5호
• /
• pp.247-260
• /
• 2022

Since the first report on ferroelectricity in Si-doped hafnia (HfO2), this emerging ferroelectrics have been considered promising for the next-generation semiconductor devices with their characteristic nonvolatile data storage. The robust ferroelectricity in the sub-10-nm thickness regime has been proven by numerous research groups. However, extending their scalability below the 5 nm thickness with low temperature processes compatible with the back-end-of-line technology. In this review, therefore, the current status, technical issues, and their potential solutions of atomic layer deposition (ALD) of HfO₂-based ferroelectrics are comprehensively reviewed. Several technical issues in the physical scaling of the ferroelectric thin films and potential solutions including advanced ALD techniques including discrete feeding ALD, atomic layer etching, and area selective ALD are introduced.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1998년도 추계학술대회 논문집
• /
• pp.267-270
• /
• 1998

We measured the dielectric properties with YMnO$_3$ ceramics using solution method based procedure via by citrate. The crystalline phases were determined using XRD. Also we observed morphologies of YMnO$_3$ ceramics using SEM. We proved the structure of YMnO$_3$ ceramics which is hexagonal. But lots of pores were observed the microstructure. It would be considered as volatile organic. The maximum density of YMnO$_3$ ceramics is obtained sintering temperature 135$0^{\circ}C$ and the ratio 0.95/1.05 of Y/Mn. But even though the density we obtained is the highest, that is lower than theoretical density because of remaining organics by citric acid. Dielectric constant and dissipation factor were improved as increasing sintering temperature and the Y/Mn ratio (0.95/1.05)

• 한국공작기계학회:학술대회논문집
• /
• 한국공작기계학회 1998년도 추계학술대회 논문집
• /
• pp.267.1-270
• /
• 1998

We measured the dielectric properties with YMnO$_3$ ceramics using solution method based procedure via by citrate. The crystalline phases were determined using XRD. Also we observed morphologies of YMnO$_3$ ceramics using SEM. We proved the structure of YMnO$_3$ ceramics which is hexagonal. But lots of pores were observed the microstructure. It would be considered as volatile organic. The maximum density of YMn03 ceramics is obtained sintering temperature 135$0^{\circ}C$ and the ratio 0.95/1.05 of Y/Mn. But even though the density we obtained is the highest, that is lower than theoretical density because of remaining organics by citric acid. Dielectric constant and dissipation factor were improved as increasing sintering temperature and the Y/Mn ratio (0.95/1.05)

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
• /
• pp.657-660
• /
• 1999

In this paper, we have investigated YMnO$_3$ bulk ceramics, which was made by Mixed oxide method, with Y/Mn ratios of 0.80/1.20, 0.90/1.10, 0.95/1.05, 1.00/1.00, 1.05/0.95 and 1.10/0.90. The samples crystall structure with Y/Mn ratios of 0.95/1.05 was hexagonal structure. The physical properties of YMnO$_3$ ceramics were divided into two groups, the sample with Y/Mn ratios of 0.80/1.20, 0.90/1.10 and 0.95/1.05 is classified to Mn rich sample, and with Y/Mn ratios of 1.00/1.00, 1.05/0.95 and 1.10/0.90 is classified to Y rich sample. The sintering and dielectric properties of this sample were summarized as following sintering density of Mn rich sample was increased. Dissipation factor of Mn rich sample was small The dielectric constant, dissipation factor of sample with Y/Mn ratio (0.90/1.10) were 37, 0.017 respectively at measured 1MHz

• 대한전자공학회논문지SD
• /
• 제39권12호
• /
• pp.1033-1044
• /
• 2002

본 논문에서는 grounded-plate PMOS 게이트 (GPPG) 강유전체 메모리 셀을 이용한 새로운 FRAM 설계기술을 제안하였다 GPPG 셀은 PMOS와 강유전체 커패시터로 구성되며 셀 plate 는 ground 에 접지 된다. 제안된 FRAM 에서는 비트라인이 V/sub DD/로 precharge 되고, negative 전압 워드라인 기법이 사용되며, negative 펄스 restore 동작을 이용한다 GPPG 셀을 이용한 FRAM 구조는 셀 plate 구동기폭 사용하지 않으므로 메모리 셀 efficiency를 극대화 할 수 있는 장점이 있다. 또한 기존의 common-plate 셀과는 달리 제안된 FRAM 구조는 데이터의 읽기 및 쓰기 동작 시 강유전체 커패시터에 V/sub DD/거 충분한 전압이 가해지므로 저 전압 동작에 제한이 없다. 아울러 제안된 FRAM 구조는 필요한 8 비트 데이터만 선택하는 column-path 회로를 사용하므로 메모리 array 전력소모를 최소화 할 수 있다. 끝으로 0.5-um, triple-well/1-polycide/2-metal 공정을 이용한 4-Mb FRAM 설계를 통해 GPPG 셀 FRAM architecture 실현 가능성을 확인하였다.

• 대한전자공학회논문지SD
• /
• 제42권10호
• /
• pp.1-8
• /
• 2005

본 논문에서는 강유전체 메모리의 셀 효율을 높이기 위해 PMOS-gating 셀을 이용한 설계기법을 기술하였다. PMOS-gating 셀은 PMOS access 트랜지스터와 강유전체 커패시터로 이루어지며 커패시터의 플레이트는 ground에 고정된다. 아울러 read/write 동작시 비트라인이 $V_{DD}$로 precharge 되고, negative 전압 워드라인 기법이 사용되며, negative 펄스 restore 동작을 이용한다. 이는 셀 플레이트 구동없이 단순히 워드라인과 비트라인만 구동하여 메모리 셀의 데이타를 저장하고 읽어낼 수 있는 설계 방식으로, 기존의 셀 플레이트를 구동하는 FRAM 대비 메모리 셀 효율을 극대화 할 수 있어, multi-megabit 이상의 집적도에서 경쟁력 있는 칩 면적 구현이 가능하다. $0.25-{\mu}m$ triple-well 공정을 적용한 2.5-V, 1-Mb FRAM 시제품 설계를 통해 제안한 설계기술을 검증하였고, 시뮬레이션 결과 48 ns의 access time, 11 mA의 동작전류 특성을 보였다. 레이아웃 결과 칩 면적은 $3.22\;mm^{2}$ 이며, 기존의 셀 플레이트 구동기를 사용하는 FRAM 대비 약 $20\;\%$의 셀 효율을 개선하였다.