• Journal of Internet Computing and Services
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• v.19 no.2
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• pp.33-41
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• 2018

In recent years, technology is rapidly changing to support new service consumption and distribution models in multimedia service systems and hybrid delivery of media services is a key factor for enabling next generation multimedia services. This phenomenon can lead to rapidly increasing network traffic and ultimately has a direct and aggravating effect on the user's quality of service (QOS). To address the issue, we propose a novel system architecture to provide smart hybrid media services efficiently. The architecture is designed to apply the software-defined networking (SDN) method, detect changes in traffic, and combine the data, including user data, service features, and computation node status, to provide a service schedule that is suitable for the current state. To this end, the proposed architecture is based on 2-level scheduling, where Level-1 scheduling is responsible for the best network path and a computation node for processing the user request, whereas Level-2 scheduling deals with individual service requests that arrived at the computation node. This paper describes the overall concept of the architecture, as well as the functions of each component. In addition, this paper describes potential scenarios that demonstrate how this architecture could provide services more efficiently than current media-service architectures.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.160-162
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• 2007

The systems for assisted living and convenience of user real-time requirement in data communication among devices. therefore, it system was requirement to implementation of the hardware which guarantees the real-time to load the high-performance processor with suitable Operation System. This paper apply to operated intelligence robot in USN(Ubiquitous Sensor Network) environment, particularly, it is architecture research for guarantees the real-time of a sink-node that collect various sensor information from sensors and sending to main control unit.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.48-58
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• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• ETRI Journal
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• v.33 no.4
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• pp.648-651
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• 2011

This letter presents a highly efficient rack-level DC power architecture combined with a node-level DC uninterruptible power supply (UPS). The proposed system can provide almost the equivalent power efficiency of a high-voltage DC data center without any change in the existing power infrastructure. The node-level DC UPS combined with a power distribution board provides high power efficiency as well as lower UPS installation costs. Implemented on a rack, the entire power system can be monitored through a network.

• Steel and Composite Structures
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• v.20 no.4
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• pp.869-887
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• 2016

The socket-spigot template supporting system is widely used in engineering applications in China. As a newer type of support structure, there has been growing research interest in its bearing capacity. In this paper, four vertical bearing capacity tests were carried out on the basic mechanical unit frame of a socket-spigot template supporting system. The first goal was to explore the influence of the node semi-rigid degree and the longitudinal spacing of the upright tube on the vertical bearing capacity. The second objective was to analyze the displacement trend and the failure mode during the loading process. This paper presents numerical analysis of the vertical bearing capacity of the unit frames using the finite element software ANSYS. It revealed the relationship between the node semi-rigid degree and the vertical bearing capacity, that the two-linear reinforcement model of elastic-plastic material can be used to analyze the socket-spigot template supporting system, and, through node entity model analysis, that the load transfer direction greatly influences the node bearing area. Finally, this paper indicates the results of on-site application performance experiments, shows that the supporting system has adequate bearing capacity and stability, and comments on the common work performance of a socket and fastener scaffold.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.215-217
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• 2004

In wireless sensor networks, fair allocation of bandwidth among different nodes is one of the critical problems that effects the serviceability of the entire system. Fair bandwidth allocation mechanisms, like fair queuing, usually need to maintain state, manage buffers, and perform packet scheduling on a per flow basis, and this complexity may prevent them from being cost-effectively implemented and widely deployed. It is a very important and difficult technical issue to provide packet scheduling architecture for fairness in wireless sensor networks. In this paper, we propose an packet scheduling architecture for sensor node, called FISN (Fairness Improvement Sensor Network), that significantly reduces this implementation complexity yet still achieves approximately fair bandwidth allocations. Sensor node for sensing estimate the incoming rate of each sensor device and insert a label into each transmission packet header based on this estimate. Sensor node for forwarding maintain no per flow state; they use FIFO packet scheduling augmented by a probabilistic dropping algorithm that uses the packet labels and an estimate of the aggregate traffic at the gathering node. We present the detailed design, implementation, and evaluation of FISN using simulation. We discuss the fairness improvement and practical engineering challenges of implementing FISN in an experimental sensor network test bed based on ns-2.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.7
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• pp.720-725
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• 2008

This paper proposes a system architecture for USN with a service robot to provide more active assisted living services for elderly persons by monitoring their mental and physical well-being with USN environments at home, hospital, or silver town. Sensors embedded in USN are used to detect preventive measures for chronic disease. Logged data are transferred to main controller of a service robot via wireless channel in which the analysis of data is performed. For the purpose of handling emergency situations, it needs real-time processing on gathering variety sensor data, routing algorithms for sensor nodes to a moving sink node and processing of logged data. This paper realized multi-hop sensor network to detect user movements with biometric data transmission and performed algorithms on Xenomai, a real-time embedded Linux. To leverage active sensing, a mobile robot is used of which task was implemented with a priority to process urgent data came from the sink-node. This software architecture is anticipated to integrate sensing, communication and computing with real-time manner. In order to verify the usefulness of a proposed system, the performance of data transferring and processing on a real-time OS with non real-time OS is also evaluated.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.165-167
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• 2006

In this paper we present a new-generation sensor network processor which is not optimized in circuit level, but in system architecture level. The new design build on a conventional processor architecture, improving the design by focusing on application oriented specification, ISA, and micro-architectural optimization that reduce overall design size and advance energy-per-instruction. The design employs harvard architecture, 8-bit data paths, and an compact 19 bit wide RISC ISA. The design also features a unique interrupt handler which offloads periodical monitoring jobs from the main part of CPU. Our most efficient design is capable of running at 300 KHz (0.3 MIPS) while consuming only about few pJ/instruction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2869-2885
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• 1996

There werer many researches on the switch system for high speed netowrk such as B-ISDN and the server system for the multimedia services respectively. But, in case of simple connection of these two systems, we have to suffer the bottlenck problem of data transmission, and pay the wasteful expenditure because of duplicated architecture of both systems such as interconnecting network at the switch and the server. Therefore, we propse the unified architecture of switehces and servers, which can be used as switches and servers simultaneously. This is based on the hybercube structure. The links are used iterconnection network of switch system, and each node has the subscriber subsystem and the server subsystem. The proposed architecure has the benifits as follows; the easy espansion of capacity due to the scalability,the simple system development and maintenance because of the equivalance of each nodes, the high reliability against the fault of nodes and links due to the existence of the many alternative links between nodes, the easy flow and QoS managment due to the non-blocking data transmission between any two nodes, the flexible adaptation for additional new services owing to simple insertion server board to node. In this paper, we present overal configuration and node component of proposed architecture, and the procesing flow for the various services.

• Journal of Korea Multimedia Society
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• v.20 no.8
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• pp.1357-1368
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• 2017

Sensor networks are used in various fields such as marine, defense, and smart home etc. Among the components of the sensor network, the sensor node collects sensor data, as one of the representative sensor network roles, and the sensor node makes a greate influence on the overall performance of the sensor network. Therefore, how to design the sensor node is an important issue in the sensor network field. However, the research on the sensor network architecture suitable for the sensor network installation environment has been made more important than the research on how to configure the sensor node. In this paper, we propose to identify elements to be considered for designing a sensor node that makes a large influence on the performance of the sensor network, and to easily implement the sensor node through the state transition model based on these elements.