• Journal of the Institute of Convergence Signal Processing
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• v.5 no.3
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• pp.230-235
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• 2004

This paper describes FPGA implementation of a pointer interpreter which can support a synchronization of SDH(or SONET)-based transmission network. The pointer interpreter consists of a pointer-word extractor and a pointer-word interpreter The pointer-word extractor which is composed of mod-6480 counter, shift register and pointer synchronizing block, finds out the H1 and H2 pointer word from a 51.84 Mb/s AU-3/STS-1 data frame and then performs the synchronizing with a 6.48 Mb/s by dividing them in 8. Based on the extracted pointer word, pointer-word interpreter analyzes pointer states such LOP, AIS and NORM according to pointer state-transition algorithm. It consists of a majority vote, a pointer word valid/invalid check, a pointer justification, and a pointer state check. The simulation results of Xilinx Virtex XCV200PQ240 FPGA chip shows the exact pointer word extraction and correct decision of pointer status based on extracted pointer word. The proposed pointer interpreter is suitable for pointer interpretation of 155 Mb/s STM-1/STS-3 frame.

• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

• International Journal of Aeronautical and Space Sciences
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• v.18 no.4
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• pp.675-687
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• 2017

In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.

• Transactions on Electrical and Electronic Materials
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• v.11 no.5
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• pp.238-241
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• 2010

The purpose of this study is to solve the problems of radio frequency bandwidth frequency depletion, confusion possibilities, and security that are in current wireless communications systems, and to confirm the possibility of applying those solutions for the next generation network. To solve the problems of the current wireless communications system, a visible light communications system for power line communication (PLC) via 8-bit microcontroller is created and the capacity is analyzed. The exclusive PLC chip APLC-485MA, an 8-bit ATmega16 microcontroller, high brightness 5pi light emitting diodes (LEDs), and the LLS08-A1 visible light-receiving sensor were used for the transmitter and receiver. The performance was analyzed using a designed program and an oscilloscope. The voltage change was measured as a function of distance from 10-50 cm. Blue LEDs showed the best performance among the measured LED types, with 0.47 V of voltage loss, but for a distance over 50 cm, precise data was not easy to obtain due to the weak light. To overcome these types of problems, specific values such as the changing conditions and efficiency value relevant to the light emitting parts and the visible light-receiving sensor should be calculated, and continuous study and improvements should also be realized for better communication conditions.

• Journal of information and communication convergence engineering
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• v.18 no.1
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• pp.1-7
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• 2020

This paper proposes a fast-processing and low-cost hardware multiple input multiple output (MIMO) channel emulator. The channel emulator is an important component of hardware-based simulation systems. The novelty of this work is the use of sharing and pipelining functions to reduce hardware resource utilization while maintaining a high sample rate. In our proposed emulator, the samples are created sequentially and interpolated to ensure the sample rate is equal to the base band rate. The proposed 4 × 4 MIMO requires low-cost hardware resource so that it can be implemented on a single field-programmable gate array (FPGA) chip. An implementation on Xilinx Virtex-7 VX980T was found to occupy 10.47% of the available configurable slice registers and 12.58% of the FPGA's slice lookup tables. The maximum frequency of the proposed emulator is 758.064 MHz, so up to 560 different paths can be processed simultaneously to generate 560 × 758 million × 2 × 32 bit complex-valued fading samples per second.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.11
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• pp.2043-2047
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• 2010

This study is to solve problems of depletion of RF bandwidth frequency, confusion possibility, security that current wireless communications system have and is to confirm possibility of applying next generation network. To solve problems of current wireless communications system, visible light communications system for power line communications using ATmega16 Microcontroller is was realized and receiver property was analyzed. PLC exclusive chip APLC-485MA, Microcontroller ATmega16, 5pi bulb type LED and high flux LED, visible light receiving sensor LLS08-A1 were used for transmitter and receiver. Performance was analyzed by designed program and an oscilloscope. It was showed average 20% improved receiver rate rather than bulb type LED in the case of high flux LED through voltage change rate on communication distance and LED type of distance between 10 to 50 cm. The blue LED showed the best performance among measured LED types with above 10% of voltage decreasing rate. But As it gradually becomes more distant, the precise date was difficult to obtain due to weak light. To overcome these sort of problems, specific values such as changing conditions and efficiency value relevant to light emitting parts and visible light receiving sensor should be calculated and continuous study and improvements should also be accomplished for the better communications condition.

• ETRI Journal
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• v.46 no.5
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• pp.829-838
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• 2024

SoCs with analog-circuit-based unsigned weight-accumulating spiking neural networks (UWA-SNNs) are a highly promising solution for achieving lowpower AI-SoCs. This paper addresses the challenges that must be overcome to realize the potential of UWA-SNNs in low-power AI-SoCs: (i) the absence of UWA-SNN learning methods and the lack of an environment for developing applications based on trained SNN models and (ii) the inherent issue of testing and validating applications on the system being nearly impractical until the final chip is fabricated owing to the mixed-signal circuit implementation of UWA-SNN-based SoCs. This paper argues that, by integrating the proposed solutions, the development of an EDA tool that enables the easy and rapid development of UWA-SNN-based SoCs is feasible, and demonstrates this through the development of the SNN eXpress (SNX) tool. The developed SNX automates the generation of RTL code, FPGA prototypes, and a software development kit tailored for UWA-SNN-based application development. Comprehensive details of SNX development and the performance evaluation and verification results of two AI-SoCs developed using SNX are also presented.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.8
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• pp.1239-1245
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• 2009

Currently, so many approaching methods are being developed to optimize the antenna size. In this paper, We fabricated Inverted-F type antenna attaching lumped components to solve the limitation of antenna size. Through experiments, a basic Inverted-F type antenna was fabricated and satisfied the adequate radiation pattern. After this, we researched the effect of antenna varied by matching circuit consist of chip type resistor, inductor, and capacitor. Using that elements, the antenna was matched at aim frequency. The proposed antenna's size is $7\;{\times}\;24\;mm$ that is very small size against the resonance frequence. Measuring the developed antenna, Its return loss was -18dB. Thus, this antenna can be used for Z-wave systems.

• Journal of electromagnetic engineering and science
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• v.4 no.4
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• pp.156-161
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• 2004

The MMIC cascode VCO is designed, fabricated, and measured for Ku-band Low Noise Blcok(LNB) system using InGaP/GaAs HBT technology. The phase noise of -116.4 dBc/Hz at 1 MHz offset with output power of 1.3 dBm is obtained at 11.526 GHz by applying 3 V and 11 mA, which is comparatively better characteristics than compared with the different configuration VCOs fabricated with other technologies. The simulated results of oscillation frequency and second harmonic suppression agree with the measured results. The phase noise is improved due to the use of the smallest value of inductor in frequency determining network and the InGaP ledge function of the technology. The chip size of $830\time781\;{\mu}m^2$ is also achieved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.6 s.109
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• pp.511-518
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• 2006

In this paper, a small RFID tag antenna in UHF band which has bandwidth-enhanced characteristic is proposed. The shape of the proposed antenna is a meander antenna to have size-reduced characteristic, and it consists of two radiators which make dual resonance in adjacent frequency to enhance bandwidth. By adjusting length and location of each radiator, the proposed antenna can make dual resonance at arbitrary location on the Smith chart, which is able to make impedance matching with RFID tag chip in wide frequency range. And it is apparent that the proposed antenna can have bandwidth-enhanced characteristic according to the simulated and measured results.