• Title/Summary/Keyword: Network Processor[1]

Search Result 145, Processing Time 0.031 seconds

Implementation of Internet Terminal using G.729.1 Wideband Speech Codec for Next Generation Network (차세대 통신망을 위한 G.729.1 광대역 음성 코덱을 활용한 인터넷 단말 구현)

  • So, Woon-Seob;Kim, Dae-Young
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.33 no.10B
    • /
    • pp.939-945
    • /
    • 2008
  • Tn this paper we described the process and the results of an implementation of Internet terminal using G.729.1 wideband speech codec for next generation network. For this purpose firstly we chose a high performance RISC application processor having DSP features for speech codec processing and enhanced Multimedia Accelerator(eMMA) function for video codec. In the implementation of this terminal, we used G.729.1 codec recently standardized in ITU-T which is a new scalable speech and audio codec that extends 0.729 speech coding standard. To adopt G.729.1 codec to this terminal we transformed most of the fixed point C codes which require more complexity into assembly codes so as to minimize processing time in the processor. As a result of this work we reduced the execution time of the original C codes about 80% and operated in real time on the terminal. For video we used H.263/MPEG-4 codec which is supported by the eMMA with hardware in the processor. In the SIP call processing test connected to real network we obtained under looms end-to-end delay and 3.8 MOS value measured with PESQ instrument. Besides this terminal operated well with commercial terminals.

Implementation of VPN Accelerator Board Used 10 Giga Security Processor (10Giga 급 보안 프로세서를 이용한 VPN 가속보드 구현)

  • Kim, Ki-Hyun;Yoo, Jang-Hee;Chung, Kyo-Il
    • Proceedings of the IEEK Conference
    • /
    • 2005.11a
    • /
    • pp.233-236
    • /
    • 2005
  • Our country compares with advanced nations by supply of super high speed network and information communication infra construction has gone well very. Many people by extension of on-line transaction and various internet services can exchange, or get information easily in this environment. But, virus or poisonous information used to Cyber terror such as hacking was included within such a lot of information and such poisonous information are threatening national security as well as individual's private life. There were always security and speed among a lot of items to consider networks equipment from these circumstance to now when develop and install in trade-off relation. In this paper, we present a high speed VPN Acceleration Board(VPN-AB) that balances both speed and security requirements of high speed network environment. Our VPN-AB supports two VPN protocols, IPsec and SSL. The protocols have a many cryptographic algorithms, DES, 3DES, AES, MD5, and SHA-1, etc.. The acceleration board process data packets into the system with In-line mode. So it is possible that VPN-AB processes inbound and outbound packets by 10Gbps. We use Nitrox-II CN2560 security processor VPN-AB is designed using that supports many hardware security modules and two SPI-4.2 interfaces to design VPN-AB.

  • PDF

Robust Terrain Classification Against Environmental Variation for Autonomous Off-road Navigation (야지 자율주행을 위한 환경에 강인한 지형분류 기법)

  • Sung, Gi-Yeul;Lyou, Joon
    • Journal of the Korea Institute of Military Science and Technology
    • /
    • v.13 no.5
    • /
    • pp.894-902
    • /
    • 2010
  • This paper presents a vision-based robust off-road terrain classification method against environmental variation. As a supervised classification algorithm, we applied a neural network classifier using wavelet features extracted from wavelet transform of an image. In order to get over an effect of overall image feature variation, we adopted environment sensors and gathered the training parameters database according to environmental conditions. The robust terrain classification algorithm against environmental variation was implemented by choosing an optimal parameter using environmental information. The proposed algorithm was embedded on a processor board under the VxWorks real-time operating system. The processor board is containing four 1GHz 7448 PowerPC CPUs. In order to implement an optimal software architecture on which a distributed parallel processing is possible, we measured and analyzed the data delivery time between the CPUs. And the performance of the present algorithm was verified, comparing classification results using the real off-road images acquired under various environmental conditions in conformity with applied classifiers and features. Experiments show the robustness of the classification results on any environmental condition.

데이터 통신을 위한 우리나라 공중교환전화망 개방과 공중교환데이타망 구성의 전망

  • 조규심
    • Journal of the Korean Professional Engineers Association
    • /
    • v.16 no.1
    • /
    • pp.4-12
    • /
    • 1983
  • Data communication has historically evolved from leased lines, to use of the public telephone network, and eventually to dedicated(exclusive) data networks. It requires an enormous amount of money for establishing a separate and independent data network at the beginning stage. No country has ever adopted this method In the Republic of Korea too the age of leased circuits is passing and it is scheduled to open the public telephone network to the data transmission and to install packet mode processor in the last half of 1983. This paper presents a survey on characteristics of the public telephone network in Seoul and a future development of the data communication of Korea.

  • PDF

Design and Implementation of Unified Hardware for 128-Bit Block Ciphers ARIA and AES

  • Koo, Bon-Seok;Ryu, Gwon-Ho;Chang, Tae-Joo;Lee, Sang-Jin
    • ETRI Journal
    • /
    • v.29 no.6
    • /
    • pp.820-822
    • /
    • 2007
  • ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.

  • PDF

Feasibility and Performance Analysis of RDMA Transfer through PCI Express

  • Choi, Min;Park, Jong Hyuk
    • Journal of Information Processing Systems
    • /
    • v.13 no.1
    • /
    • pp.95-103
    • /
    • 2017
  • The PCI Express is a widely used system bus technology that connects the processor and the peripheral I/O devices. The PCI Express is nowadays regarded as a de facto standard in system area interconnection network. It has good characteristics in terms of high-speed, low power. In addition, PCI Express is becoming popular interconnection network technology as like Gigabit Ethernet, InfiniBand, and Myrinet which are extensively used in high-performance computing. In this paper, we designed and implemented a evaluation platform for interconnect network using PCI Express between two computing nodes. We make use of the non-transparent bridge (NTB) technology of PCI Express in order to isolate between the two subsystems. We constructed a testbed system and evaluated the performance on the testbed.

Design and Implementation of an Edge Router having ATM and Ethernet Interfaces using the Programmable Ethernet Packet Processor (프로그램 가능한 이더넷 패킷 프로세서를 이용한 ATM과 Ethernet 인터페이스를 갖는 에지 라우터의 설계 및 구현)

  • Park, Jae-Hyung;Kim, Mi-Hee;Lee, Yoo-Kyung
    • The KIPS Transactions:PartC
    • /
    • v.9C no.6
    • /
    • pp.903-910
    • /
    • 2002
  • As the edge router provides the facility that it is capable of interworking with various kinds of networks, the forwarding engine should have the flexibility processing the corresponding types of frames from such network interfaces. In order to support the flexibility, we design and implement a prototype of edge router with ATM and Ethernet interfaces based on the programmable Ethernet packet processor Our forwarding engine handles and forwards the frames from ATM interfaces by using loop-back functionality of Ethernet packet processor. The performance of our edge router is evaluated by experiments throughout its performance of forwarding engine and tested by interworking with another kinds of routers.

A Study on the Implementation of Hopfield Model using Array Processor (어레이 프로세서를 이용한 홉필드 모델의 구현에 관한 연구)

  • 홍봉화;이지영
    • Journal of the Korea Society of Computer and Information
    • /
    • v.4 no.4
    • /
    • pp.94-100
    • /
    • 1999
  • This paper concerns the implementation of a digital neural network which performs the high speed operation of Hopfield model's arithmetic operation. It is also designed to use a look-up table and produce floating point arithmetic of nonlinear function with high speed operation. The arithmetic processing of Hopfleld is able to describe the matrix-vector operation, which is adaptable to design the array processor because of its recursive and iterative operation .The proposed method is expected to be applied to the field of real neural networks because of the realization of the current VLSI techniques.

  • PDF

Design of Hybrid Controller Using Neural Network-Fuzzy (신경망-퍼지 하이브리드 제어기 설계)

  • 신위재
    • Journal of the Institute of Convergence Signal Processing
    • /
    • v.3 no.1
    • /
    • pp.54-60
    • /
    • 2002
  • In this paper, we proposed a hybrid neural network-fuzzy controller which compensate a output of neural network controller. Even if learn by neural network controller, it can occur an bad results from disturbance or load variations. So in order to adjust above case, we used the fuzzy compensator to get an expected results. And the weight of main neural network can be changed with the result of loaming a inverse model neural network of Plant, so a expected dynamic characteristics of plant can be got. As the results of simulation through the second order plant, we confirmed that the proposed speed controller get a good response compare with a neural network controller. We implemented the controller using the DSP processor and applied in a hydraulic servo system. And then we observed an experimental results.

  • PDF

A Distributed Algorithmfor Weighted Shortest Path Problem (최단경로문제를 해결하는 효율적인 분산 알고리즘)

  • Park, Jeong-Ho;Park, Yun-Yong
    • The Transactions of the Korea Information Processing Society
    • /
    • v.6 no.1
    • /
    • pp.42-48
    • /
    • 1999
  • Consider the situation that informations necessary to solve a certain problem are distributed among processors on a network. It is called a distributed algorithm that in this situation each processor exchanges the message with adjacent processors to solve the problems. This paper proposes a distributed algorithm to solve the problem that constructs the weighted shortest path tree in an asynchronous network system. In general, a distributed algorithm is estimated by the number of messages(message complexity of the distributed algorithm proposed in this paper are O(n53) and O(nln) respectively. where n is the number of processors on the network.

  • PDF