• Journal of Korea Society of Industrial Information Systems
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• v.18 no.4
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• pp.9-18
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• 2013

Flash memory is mostly used on smart devices and embedded systems because of its nonvolatile memory, low power, quick I/O, resistant shock, and other benefits. Generally the typical file systems base on the NAND flash memory are YAFFS2, JFFS2, UBIFS, and etc. In this paper, we had variously made an experiment regarding I/O performance using our schemes and the UBIFS of the latest Linux Kernel. The proposed I/O performance analyses were classified as a sequential access and a random access. Our experiment consists of 6 cases using kmalloc(), vmalloc(), and kmem_cache(). As a result of our experiment analyses, the sequential reading and the sequential rewriting increased by 12%, 11% when the Case 2 has applied vmalloc() and kmalloc() to the UBI subsystem and the UBIFS. Also, the performance improved more by 7.82%, 6.90% than the Case 1 at the random read and the random write.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.5
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• pp.322-330
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• 2009

In order to utilize NAND flash memory as storage media which does not allow update-in-place and limits the number of block erase count, various garbage collection policies supporting wear-leveling have been investigated. Conventional garbage collection policies require cleaning-index calculation for the entire blocks to choose a block to be garbage-collected to support wear-leveling whenever a garbage collection is required, which results in performance degradation of system. This paper proposes a garbage collection policy which supports wear-leveling using a threshold value, which is in fact a variance of erase counts and by the maximum erase count of all blocks, without calculating the cleaning-index. During garbage collection, the erase cost is minimized by using the Greedy Policy if the variance is less than the threshold value. It achieves wear-leveling by excluding the block with the largest erase count from erase target blocks if the variance is larger than threshold value. The proposed scheme shows that a standard deviation approaches to zero as the erase count of blocks approaches to its upper limit and the measured speed of garbage collection is two times faster than the conventional schemes.

• Journal of Internet of Things and Convergence
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• v.8 no.5
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• pp.77-83
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• 2022

Nand flash memory requires an Erase-Before-Write operation structurally. In order to solve this problem, it can be solved by classifying a page (hot data page) where data update operation occurs frequently and storing it in a separate block. The MHF (Multi Hash Function Framework) technique records the frequency of data update requests in the system memory, and when the recorded value exceeds a certain standard, the data update request is judged as hot data. However, the method of simply counting only the frequency of the data update request has a limit in judging it as accurate hot data. In addition, in the case of a technique that determines the persistence of a data update request, the fact of the update request is recorded sequentially based on a time interval and then judged as hot data. In the case of such a persistence-based method, its implementation and operation are complicated, and there is a problem of inaccurate judgment if frequency is not considered in the update request. This paper proposes a lightweight hot data determination technique that considers both frequency and persistence in data update requests.

• Journal of Internet of Things and Convergence
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• v.8 no.5
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• pp.33-39
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• 2022

A storage device used in the mobile computing field should have low power, light weight, durability, etc., and should be able to effectively store and manage large-capacity data generated by users. NAND flash memory is mainly used as a storage device in the field of mobile computing. Due to the structural characteristics of NAND flash memory, it is impossible to overwrite in place when a data update request is made, so it can be solved by accurately separating requests that frequently request data update and requests that do not, and storing and managing them in each block. The classification method for such a data update request is called a hot data identification method, and various studies have been conducted at present. This paper continuously records the occurrence of data update requests using a counting filter for more accurate hot data validation, and also verifies hot data by considering how often the requested update requests occur during a specific time.

• Journal of Internet of Things and Convergence
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• v.10 no.2
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• pp.125-130
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• 2024

With the rapid growth of mobility technology, the industrial sector is demanding storage devices that can reliably process data from various equipment and sensors in vehicles. NAND flash memory is being utilized as a storage device in mobility environments because it has the advantages of low power and fast data processing speed as well as strong external shock resistance. However, flash memory is characterized by data corruption due to long-term exposure to high temperatures. Therefore, a dedicated system for temperature management is required in mobility environments where high temperature exposure due to weather or external heat sources such as solar radiation is frequent. This paper designs a dedicated temperature management system for managing storage device temperature in a mobility environment. The designed temperature management system is a hybrid of traditional air cooling and water cooling technologies. The cooling method is designed to operate adaptively according to the temperature of the storage device, and it is designed not to operate when the temperature step is low to improve energy efficiency. Finally, experiments were conducted to analyze the temperature difference between each cooling method and different heat dissipation materials, proving that the temperature management policy is effective in maintaining performance.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.47-52
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• 2017

This research scrutinizes the data retention characteristics of the MLC NAND Flash Memory instigated by the loss effect of trapped charge when the memory is in the state of program saturation. It is attributed to the threshold voltage saturation phenomenon which engenders an interruption to the linear increase of the voltage in the memory cell. This phenomenon is occasioned by the outflow of the trapped charge from the floating gate to the control gate, which has been programmed by the ISPP (Incremental Step Pulse Programming), via Inter-Poly Dielectric (IPD). This study stipulates the significant degradation of thermal retention characteristics of threshold voltage in the saturation region in contrast to the ones in the linear region. Thus the current study evaluates the data retention characteristics of voltage after the program with a repeated reading test in various measurement conditions. The loss effect of trapped charge is found in the IPD layer located between the floating gate and the control gate especially in the nitride layer of the IPD. After the thermal stress, the trapped charge is de-trapped and displays the impediment of the characteristic of reliability. To increase the threshold saturation voltage in the NAND Flash Memory, the storage ability of the charge in the floating gate must be enhanced with a well-thought-out designing of the module in the IPD layer.

• Journal of Advanced Navigation Technology
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• v.13 no.4
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• pp.509-514
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• 2009

In this paper, we designed and analyzed 256GB DRAM-based SSD storage using DDR1 memory and PCI-e interface. SSD is a storage system that uses DRAM or NAND Flash as primary storage media. Since the SSD read and write data directly to memory chips, which results in storage speeds far greater than conventional magnetic storage devices, HDD. Architecture of the proposed SSD system has performance of high speed data processing duo to use multiple RAM disks as primary storage and PCI-e interface bus as communication path of RAM disks. We constructed experimental system with UNIX, Windows/Linux server, SAN Switch, and Ethernet Switch and measured IOPS and bandwidth of proposed SSD using IOmeter. In experimental results, it has been shown that IOPS, 470,000 and bandwidth,800MB/sec of the DDR-1 SSD is better than those of the HDD and Flash-based SSD.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.6
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• pp.383-391
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• 2011

As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06c
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• pp.88-91
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• 2011

NAND 플래시 메모리는 저전력과 빠른 접근 속도의 특징 때문에 차세대 저장장치로 주목 받고 있다. 특히 플래시 메모리로 만들어진 SSD(solid state disk)는 인터페이스가 기존의 하드디스크와 동일하고 대용량화 되고 있기 때문에 가까운 미래에 다양한 저장시스템의 저장장치로 사용될 것으로 예상된다. 그러나 NAND 플래시메모리 기반 저장장치는 쓰기 전 소거 구조와 같은 독특한 하드웨어 특징을 가지고 있기 때문에 특정 지역에 반복적인 쓰기 요청을 발생하는 B트리를 구축하는 것은 심각한 성능저하를 야기 할 것이다. 이러한 문제를 해결하기 위해 버퍼를 이용하여 B트리 구축 성능을 개선한 방법들이 제안되었다. 그러나 이러한 기법들은 갑작스러운 전원 차단 시 버퍼에 유지하고 있던 데이터를 모두 유실하기 때문에 고장회복을 위한 추가적인 방법이 필요하다. 따라서 본 논문에서는 버퍼를 이용한 방법 중 IBSF기법을 기반으로 NAND 플래시 메모리 기반 저장장치에서 고성능의B트리 구축 방법뿐만 아니라 전원 차단시 효율적인 고장회복을 할 수 있는 기법을 제안한다. 본 논문에서 제안하는 기법은 B트리 변경시 변경 된 정보를 로그에 저장하여 관리한다. 또한 루트노드가 변경될 때 검사점(checkpoint)을 수행한다. 마지막으로 다양한 실험을 통하여 본 논문의 고장회복 성능을 보여준다.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.05a
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• pp.204-207
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• 2008

NAND 플래시 메모리는 하드 디스크에 비해 작고, 빠르며, 저 전력 소모 등과 같은 장점을 가지고 있어 대체 저장 매체로 주목받고 있다. 그러나 제자리 갱신이 불가능한 특징을 가지고 있어 B-트리를 사용하면 갱신이 빈번하게 발생하여 읽기 연산에 비해 상대적으로 느린 쓰기 연산과 소거 연산이 빈번해져 시스템의 성능이 저하 된다. 이러한 성능 저하를 피하기 위해 $\mu}$-트리가 제안되었으나, 고정된 페이지 레이아웃 구조를 가지고 있어 노드 분할과 트리 신장이 빈번하게 일어난다. 본 논문에서는 NAND 플래시 메모리 상에서 B-트리 구현 시 발생하는 추가적인 쓰기 연산의 횟수를 줄이기 위해 갱신이 일어나는 단말 노드에 로그 노드를 할당하여, 갱신되는 내용을 저장한다. 따라서 부모 노드의 내용이 변경 되는 것을 늦추어 추가적인 쓰기 연산을 줄이게 되며, 순차적인 키 값의 삽입이나 일정 노드에 대한 빈번한 갱신은 로그 노드가 단말 노드로 전환되어 추가적인 쓰기 연산을 줄이게 된다. 이러한 방법으로 추가적인 쓰기 연산을 줄임으로써 시스템의 성능을 향상시키는 NAND 플래시 메모리를 위한 새로운 B-트리 구조를 제안한다.