• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.8
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• pp.430-435
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• 2006

This paper presents a method about the efficiency analysis and the harmonic reduction of single phase NPC multi-level inverter with LC-trap filter and LCR output filter. The proposed LC-trap filter is comprised of a conventional LC output filter, by using LC-trap filter the need for high damping resistor and low LC cut-off frequency is eliminated. Also, low damping resistor is increased the efficiency of the output filter. Experimental verification of the proposed circuit is provided with single phase NPC multilevel inverter system and DSP controller.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.376-382
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• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.173-183
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• 2014

In this paper, an analysis of power losses for the three-level T-type and neutral-point clamped (NPC) PWM inverters is presented, in which the conduction and switching losses of semiconductor devices of the inverters are taken into account. In the inverter operation, the conduction loss depends on the modulation index (MI) and power factor (PF), whereas the switching loss depends on the switching frequency. Power losses for the T-type and NPC inverters are analyzed and calculated at the different operating points of MI, PF and the switching frequency, in which the four different models of semiconductor devices are adopted. In the case of lower MI, the NPC-type is more efficient than the T-type, and vice versa. The validity of the power loss analysis has been verified by the simulation results.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.6
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• pp.535-540
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• 2022

DC-link capacitors are reliability-critical components in a photovoltaic (PV) inverter. Typically, the lifetime of a DC-link capacitor is evaluated by considering the voltage and hot-spot temperature of the capacitor under the specific operating condition of the PV inverter. However, the output of the PV inverter is determined by solar irradiation and ambient temperature, which vary with the seasons; accordingly, the hot-spot temperature of the capacitor also changes. Therefore, the mission profile of the PV system should be considered to effectively evaluate the reliability of the DC-link capacitor. In this study, the reliability of the DC-link capacitor of a three-level NPC inverter is comparatively analyzed with and without considering the mission profiles of the PV system, where two mission profiles recorded in Arizona and Iza are considered. The accumulated damage of the DC-link capacitor is calculated based on the lifetime model by analyzing its thermal loading. Afterward, a reliability evaluation of the DC-link capacitor is performed at the component level and then at the system level by considering all capacitors by means of Monte Carlo analysis. Results reveal the importance of performing a mission-profile-based reliability evaluation during the design of high-reliability PV inverters to achieve the target reliability performance.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.1
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• pp.22-32
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• 2008

This paper proposes a linearization technique for the 3-level NPC type inverter, which increases the linear control range of Inverter up to the one-pulse inverter. The overmodulation range is divided into two modes depending on the Modulation Index, MI. In overmodulation region I, the reference angles are derived from the fourier series expansion of the reference voltage corresponding to the MI. In overmodulation region II, the holding angles are also derived in the same way. Therefore, it is possible to obtain the linear control and the maximized utilization of PWM inverter output voltage.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.5
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• pp.778-785
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• 2017

This paper presents a control method for reducing the distortion of the grid current at a grid-connected three-level neutral point clamped (NPC) inverter. The grid current is distorted from the 5th and 7th harmonic components in the stationary frame current also the 6th harmonic component in the synchronous frame current. In this paper, the 6th harmonic component on synchronous frame is controlled by using all-pass filters (APFs) and proportional integral (PI) controllers for distortion of the grid side. When transformed the 6th harmonic component is controlled, the 5th and 7th harmonic components are reduced. The validity of the proposed control method is verified by simulation and experiment results using a 25kW three-level NPC inverter.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1963-1965
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• 1998

In this paper, a new simplified configuration for a multi-level PWM inverter is proposed. The proposed inverter consists of an auxiliary circuit with one switching device, and 3 phase full-bridge inverter. The proposed inverter, in spite of reduction of the switching devices, offers characteristics similar to the NPC(Neutral - point - clamped)- PWM inverter. Also, since the reduction of the switching devices, the control strategy is simplified. And switching loss is reduced. In addition to, it is possible that reliable DC level voltage than former multi-level inverter. And load power application is same to conventional NPC-PWM inverter. The performance of the system is verified by simulation. In this paper, show the simulation result of the single phase full bridge inverter application.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.1
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• pp.9-14
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• 2008

Since they use the low switching frequency in multilevel inverter systems, they generate the high low frequency harmonic components. Generally, LC filter is used at the output terminal of inverter systems to solve this problem. But it causes a voltage drop at the output terminal by use of damping resistors, and causes the problem in which system efficiency decreases due to power loss of the damping resistor. In this paper, we proposed an output filter design method for NPC three-level inverter systems with low switching frequency. And we analyzed the efficiency of the proposed filter system, and the effectiveness of the proposed system is verified by simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• v.8 no.3
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• pp.544-558
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• 2013

This paper proposes a simplified and efficient control scheme for Unified Power Quality Conditioner (UPQC) based on three-level (NPC) inverter capable to mitigate source current harmonics and compensate all voltage disturbances perturbations such us, voltage sags, swells, unbalances and harmonics. The UPQC is designed by the integration of series and shunt active filters (AFs) sharing a common dc bus capacitor. The dc voltage is maintained constant using proportional integral voltage controller. The shunt and series AF are designed using a three-phase three-level (NPC) inverter. The synchronous reference frame (SRF) theory is used to get the reference signals for shunt and the power reactive theory (PQ) for a series APFs. The reference signals for the shunt and series APF are derived from the control algorithm and sensed signals are injected in tow controllers to generate switching signals for series and shunt APFs. The performance of proposed UPQC system is evaluated in terms of power factor correction and mitigation of voltage, current harmonics and all voltage disturbances compensation in three-phase, three-wire power system using MATLAB-Simulink software and SimPowerSystem Toolbox. The simulation results demonstrate that the proposed UPQC system can improve the power quality at the common connection point of the non-linear load.

• Journal of the Korean Society for Railway
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• v.15 no.2
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• pp.129-134
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• 2012

In this paper, speed control of IPMSM drives for the next generation domestic high speed railway system using NPC 3-level inverters is presented. The NPC multilevel inverter is suitable for the high-voltage and high-power motor drive system because it has advantages in that the voltage rating of the power semiconductor devices and output current harmonics are reduced. For the speed control of IPMSM using NPC 3-level inverters, maximum torque control is applied in the constant torque region, and filed weakening control is applied in the constant power region. Simulation programs based on MATLAB/Simulink are developed. Finally the designed system is verified and their characteristics are analyzed by the simulation results.