• Journal of Power Electronics
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• v.19 no.1
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• pp.146-157
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• 2019

The inverter is an essential part of permanent magnet synchronous motor (PMSM) drive systems. The performance of an inverter is greatly influenced by its modulation strategy. Using a proper management of modulation strategies can guarantee high performance from a PMSM under various speed conditions. Switching between modulations is a pivotal technique that determines the performance of a PMSM. Most works on hybrid methods focus on two-level induction motors drive systems. In this paper, in order to improve the performance of PMSMs under various speed conditions, a hybrid method of a pulse width modulation (PWM) control scheme based on a neutral-point-clamped (NPC) three level topology was proposed. This hybrid PWM modulation comprised space vector PWM (SVPWM) and selective harmonic elimination PWM (SHEPWM). Under low speed conditions, the SVPWM is employed to cause the PMSM to start smoothly, and to obtain a rapid response from the control system. Under high speed conditions, the SHEPWM is employed to reduce the switching frequency and to eliminate particular current harmonics. Moreover, the harmonic characteristics of different modulations are analyzed to obtain a smooth transition between the SHEPWM and the SVPWM. Experimental and simulation results indicated the effectiveness of the proposed control method.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.112-113
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• 2013

본 논문에서는 부트스트랩 게이트 드라이브 회로가 적용된 3-레벨 NPC 인버터의 전동기 저속 운전에 적용하기 위한 PWM 스위칭 전략을 제안한다. 3-레벨 NPC 인버터를 이용하여 전동기를 제어할 경우, 일반적으로 구현의 편리성 때문에 CBPWM이 주로 사용된다. CBPWM 중 Unipolar 방법이 주로 사용되지만 부트스트랩 회로를 적용한 3-레벨 NPC 인버터의 전동기 저속 운전 시 부트스트랩 캐패시터 방전에 의한 전압 감소 크기가 증가한다. 캐패시터 전압이 정상적인 인버터 동작을 위한 한계 전압 이하로 감소하면 정상적인 제어는 불가능하다. 따라서 본 논문에서는 부트스트랩 회로가 적용된 3-레벨 NPC 인버터의 전동기 저속 운전에 적용하기 위한 PWM 스위칭 전략에 대해 제안 하였으며 시뮬레이션을 통하여 그 타당성을 증명하였다.

• Journal of Power Electronics
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• v.17 no.4
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• pp.923-932
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• 2017

This paper proposes a novel scheme which can compensate the common-mode voltage (CMV) for five-level active neutralpoint clamped (5L-ANPC) inverters, which is based on modifying the space vector pulse width modulation (SVPWM) and adding an auxiliary leg to the inverter. For the modified SVPWM, only the 55 voltage vectors producing low CMV values among the 125 possible voltage vectors are utilized, which varies over the three voltage levels of $-V_{dc}/12$, 0 V, and $V_{dc}/12$. In addition, the compensating voltage, which is injected into the 5L-ANPC inverter system to cancel the remaining CVM through a common-mode transformer (CMT) is generated by the additional NPC leg. By the proposed method, the CMV of the inverter is fully eliminated, while the utilization of the DC-link voltage is not decreased at all. Furthermore, all of the DC-link and flying capacitor voltages of the inverter are well controlled. Simulation and experimental results have verified the validity of the proposed scheme.

• Journal of Power Electronics
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• v.11 no.4
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• pp.583-590
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• 2011

Three-level NPC inverters have been put into practical use for years especially in high voltage high power grids. This paper researches three-level active power filters (APFs). In this paper a mathematical model in the d-q coordinates is presented for 3-phase 3-wire NPC APFs. The deadbeat control scheme is obtained by using state equations. Canceling the delay of one sampling period and providing the predictive value of the harmonic current is a key problem of the deadbeat control. Based on this deadbeat control, the predictive output current value is obtained by the state observer. The delay of one sampling period is remedied in this digital control system by the state observer. The predictive harmonic command current value is obtained by the repetitive predictor synchronously. The repetitive predictor can achieve a better prediction of the harmonic current with the same sampling frequency, thus improving the overall performance of the system. The experiment results indicate that the steady-state accuracy and the dynamic response are both satisfying when the proposed control scheme is implemented.

• Journal of Power Electronics
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• v.12 no.2
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• pp.344-356
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• 2012

In recent years, multilevel technology has become an effective and practical solution in the field of moderate and high voltage applications. This paper discusses an APF with a three-level NPC inverter. Obviously, the application of such converter to APFs is hindered by the problem of the voltage unbalance of DC capacitors, which leads to system instability. This paper comprehensively analyzes the theoretical limitations of the neutral-point voltage balancing problem for tracking different harmonic currents utilizing current switching functions from the space vector PWM (SVPWM) point of view. The fluctuation of the neutral point caused by the load currents of certain order harmonic frequency is reported and quantified. Furthermore, this paper presents a close-loop digital control algorithm of the DC voltage for this APF. A PI controller regulates the DC voltage in the outer-loop controller. In the current-loop controller, this paper proposes a simple neutral-point voltage control method. The neutral-point voltage imbalance is restrained by selecting small vectors that will move the neutral-point voltage in the direction opposite the direction of the unbalance. The experiment results illustrate that the performance of the proposed approach is satisfactory.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1415-1425
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• 2016

This paper presents a new approach for fault diagnosis in three-level neutral point clamped inverters. The proposed method is based on the average values of the positive and negative parts of normalized output currents. This method is capable of detecting and locating multiple open-circuit faults in the controlled power switches of converters in half of a fundamental period of those currents. The implementation of this diagnostic approach only requires two output currents of the inverter. Therefore, no additional sensors are needed other than the ones already used by the control system of a drive based on this type of converter. Moreover, through the normalization of currents, the diagnosis is independent of the load level of the converter. The performance and effectiveness of the proposed diagnostic technique are validated by experimental results obtained under steady-state and transient conditions.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.7-11
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• 2017

This paper describes a design concept of NPC1 power stack for 1500VDC megawatt level solar inverter. This stack uses three latest half-bridge IGBT modules with highest power density and operation junction temperature, which enable realization of power level beyond 1MW without paralleling. Critical design concept on loop inductance is explained. Dynamic characteristics are verified by double-pulse test. Thermal characteristics and output power limits are verified by thermal test. Temperature-sensitive component on PCB as output power constraint is identified. Different PCB repositioning solutions are tested to give the overall output power thermal derating curves, which enable output power of 1.15MW at $T_A=55^{\circ}C$ with $15^{\circ}C$ thermal margin. The power stack characteristic and performance change under different thermal environment is further analyzed.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2109-2118
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• 2016

Based on the space vector pulse width modulation (SVPWM) theory, this paper realizes an easier SVPWM strategy, which is equivalently implemented by CBSPWM with zero-sequence voltage injection. The traditional SVPWM strategy has no effect on controlling the neutral-point voltage balance. In order to solve the neutral-point voltage unbalance problem for neutral-point-clamped (NPC) three-level inverters, this paper proposes a neutral-point voltage balance controller. The proposed controller realizes controlling the neutral-point voltage balance by dynamically calculating the offset superimposed to the three-phase modulation waves of an equivalent SVPWM strategy. Compared with the traditional SVPWM strategy, the proposed neutral-point voltage balance controller has a strong ability to balance the neutral-point voltage, has good steady-state performance, improves the output waveforms quality and is easy for digital implementation. An experiment has been carried out on a NPC three-level inverter prototype based on a digital signal processor-complex programmable logic device (DSP-CPLD). The obtained experimental results verify the effectiveness of the proposed neutral-point voltage balance controller.

• Journal of Power Electronics
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• v.18 no.1
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• pp.70-80
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• 2018

A novel strategy based on a zero common mode voltage pulse-width modulation (ZCMV-PWM) technique and zero-sequence circulating current (ZSCC) feedback control is proposed in this study to eliminate ZSCCs between three-level neutral point clamped (NPC) voltage source inverters, with common AC and DC buses, that are operating in parallel. First, an equivalent model of ZSCC in a three-phase three-level NPC inverter paralleled system is developed. Second, on the basis of the analysis of the excitation source of ZSCCs, i.e., the difference in common mode voltages (CMVs) between paralleled inverters, the ZCMV-PWM method is presented to reduce CMVs, and a simple electric circuit is adopted to control ZSCCs and neutral point potential. Finally, simulation and experiment are conducted to illustrate effectiveness of the proposed strategy. Results show that ZSCCs between paralleled inverters can be eliminated effectively under steady and dynamic states. Moreover, the proposed strategy exhibits the advantage of not requiring carrier synchronization. It can be utilized in inverters with different types of filter.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.63-64
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• 2011

The inevitable calculation time delay of digital controller especially degrades the voltage control performance of three-phase UPS systems. This paper proposes time delay compensators based on the Smith-predictor for both voltage and current controllers of three-level NPC inverters. The PSIM-based simulation results show that the proposed controller with delay compensator gives improved voltage control performance with respect to time delay.