• Journal of the Korean Society for Precision Engineering
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• v.20 no.12
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• pp.25-33
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• 2003

A burr has been defined as undesirable projection of material formed as a result of plastic flow from a cutting or shearing operation. It is unavoidable in all kinds of machining operation. As a result, burr makes troubles on manufacturing process due to deburring cost, quality of products and productivity. In this study, the primary interest is about exit burr. The burr formation mechanism in each type of burr is classified. Data bases are developed to predict burr formation result. In the milling operation, we develop an algorithm to analyze the burr formation mechanism by the geometrical analysis on the multi featured workpiece with multi cutting path. The algorithm includes three steps, i. e., the feature identification, the cutting condition identification, and the analysis on exit burr formation. We can predict which portion of workpiece would have the exit burr in advance so that we can manage to find a way to minimize the exit burr formation in an actual cutting. Also, this algorithm can be implemented in a commercial CAM package so that we can simulate the NC code to review the burr formation in advance.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2004.11a
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• pp.862-865
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• 2004

The system air conditioner has an outdoor unit and a number of indoor units, which connected by several long pipes. In comparison with building HAVC system, the system air conditioner doesn't need lots of facilities, such as control of room, cooling tower, etc. At the beginning stage for the market of the system air conditioner, its main application was a school which size is small to use the building HAVC and large to use home air conditioning system, such as PAC (package air conditioner), RAC (room air conditioner). Therefore, because of the advantages of the system air conditioner mentioned above, the market is expanded rapidly. Since it is difficult to evaluate the noise caused by the system air conditioner because it has to be implemented before the finish of construction, the prediction or estimation of the noise by using CAE technology should be very important. In this research, using a commercial code, RAYNOISE, the noise is estimated to improve the design of building.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of the Korean Society of Safety
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• v.35 no.3
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• pp.96-104
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• 2020

The numerical simulations were conducted to investigate the thermal-fluid phenomena occurred inside the experimental apparatus during a PCCS, used to remove heat released in accidents from a containment of light water nuclear power plant, operation. Numerical simulations of the flow and heat transfer caused by wall condensation inside the containment simulation vessel (CSV), which equipped with 18 vertical heat exchanger tubes, were conducted using the commercial computational fluid dynamics (CFD) software ANSYS-CFX. Shear stress transport (SST) and the wall condensation model were used for turbulence closure and wall condensation, respectively. The simulation using the actual size of the apparatus. However, rather than simulating the whole experimental apparatus in consideration of the experimental cases, calculation resources, and calculation time, the simulation model was prepared only in CSV. Selective simulation was conducted to verify the effects of non-condensable gas(NC gas) concentration, CSV internal pressure, and wall sub-cooling conditions. First, as a result of the internal flow of CSV, it was observed that downward flow due to condensation occurred surface of the vertical tube and upward flow occurred in the distant place. Natural convection occurred actively around the heat exchanger tube. Due to this rising and falling internal flow, natural circulation occurred actively around the heat exchanger tubes. Next, in order to check the performance of built-in condensation model using according to the non-condensable gas concentration, CSV internal flow and wall sub-cooling, the heat flux values were compared with the experimental results. On average, the results were underestimated with and error of about 25%. In addition, the influence of CSV internal pressure and wall sub-cooling was small, but when the condensate was highly generated due to the low non-condensable gas concentration, the error was large compared to the experimental values. This is considered to be due to the nature of the condensation model of the CFX code. However, in spite of the limitations of CFD, it is valid to use the built-in condensation model of CFD for PCCS performance prediction from a conservative perspective.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.16 no.4
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• pp.127-134
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• 2017

A rotary table is a positioning device used in metalworking for the multiple axes of machine tools, and the utilization trend is increasing with machining efficiency. In the construction of a rotary table, the core technology is a power transfer unit that drives the table, typically a gear type and a roller gear cam type. As the rollers installed on the turret column have rolling movement on the contact surface of the roller gear cam, the roller gear cam type has the advantage of low wear, high load, and fast driving. Therefore, it is currently being replaced by a roller gear cam type. In this study, we researched a 5-axis machining method for the roller gear cam on a rotary table and a new method of applying double roller gear cam curve to reduce the noise and shock between the roller and the cam surface. We implemented the 5-axis machining process in this study using software to generate NC-code and machined the roller gear cams using a Mazak Integrex-200IV. We found that the roller gear cam and turret were able to identify mutual touch status and the noise from the operation of the roller gear cam was substantially reduced.

• 대한공업교육학회지
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• v.32 no.1
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• pp.93-116
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• 2007

The purpose of this study was to improve the academic achievement at the public practical center of technical high school in Busan. For this study, 1 class(31 students) in the second grade at "B"technical high school were selected and these students were divided into two groups. One is the experiment group which blended learning was applied to and the other is control group which traditional lecture method was applied to. Each group was divided into three sub-groups by the level of learning ability. Non-randomized control-group pretest-posttest design was applied for this experiment planning. The subject of experiment was the unit of "3D Modeling and Making NC code" in the textbook of "Application of Automatic System" applied by the public practical center of technical high school in Busan. On-line contents were developed and applied to the blended learning to control group. In order to analyze the test result, t-test with a significance level of 0.05 was carried out using SPSS 10.0. The results of this study was summarized as follows; First, as a result of the post test performed on the experiment and the control group, there was a significant difference between two groups, that was, the blended learning was more effective than the traditional lecture method in improving academic achievement. Second, blended learning was more effective than the traditional lecture method in the group of high-leveled and middle-leveled, but was little effective on the low-leveled group. Third, blended learning was more effective than the traditional lecture method in the functional domain, but was little effective in the cognitive domain and psychomotor domain.

• The Magazine of the IEIE
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• v.28 no.7
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• pp.49-55
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• 2001

1970년대에 개발된 마이크로 프로세서는 제어기기 분야 및 소형 컴퓨터에서 주로 사용되어 오다가 1980년대에 이르러 RISC(Reduced Instruction Set Computer) 구조의 도입으로 중대형 컴퓨터에 이르기까지 광범위하게 사용되고 있다. 또한 반도체 기술의 급격한 발전으로 슈퍼스칼라 구조가 마이크로 프로세서에서도 적용되고 있으며 동작 속도도 수백 MHz에 이르고 있다. 마이크로 프로세서는 프로그램을 수행하기 위해서 프로그램과 데이터를 메모리로부터 읽어 와야 한다. 그런데 메모리 용량은 빠른 속도로 증가하고 있지만 동작 속도는 마이크로 프로세서의 동작 속도에 크게 미치지 못하고 있다. 1980년에 DRAM의 접근 속도는 250nsec이었으나 1998년에 RDRAM의 동작속도는 300MHz로 70여배 빨라졌다. 그러나 마이크로프로세서는 1980년에 8086의 동작 속도가 8MHz이던 것이 1998년에는 팬티엄-2가 500MHz에 이르고 있다. 더욱이 팬티엄-2는 슈퍼스칼라 구조이므로 이를 감안하면 1GHz 이상에 이르러 120여 배 빨라진 것을 알 수 있다. 이와 같은 메모리 속도와 마이크로 프로세서 속도 차이에 더하여, 메모리와 마이크로 프로세서를 인쇄 회로 기판에서 연결하는데 따른 물리적 특성은 변화하지 않으므로 데이터 전송 폭을 넓히는 것에는 한계가 있다. 따라서 향후 컴퓨터 성능 발달을 제한하는 주요 요소 중 하나는 마이크로 프로세서와 메모리 사이의 데이터 전송 폭이다. 프로그램과 데이터가 메모리에 저장되는 본 뉴먼 방식의 컴퓨터에서 데이터 전송 폭을 줄이기 위해서는 코드 밀도(Code Density)가 높은 컴퓨터 구조를 연구하는 것이 필요하다. 한편 마이크로 프로세서는 실장 제어용으로 거의 모든 전자 제품 및 자동화 기기에서 채용하고 있다. 특히 냉장고, 에어콘, 전축, TV, 세탁기 등 가전기기와 Fax, 복사기, 프린터 등 사무용기기와 자동차, 선박, 자동화기계 등 사무 및 산업용 기기와 PDA(휴대용 정보 기기), NC(Network Computer) 등 정보 기기 그리고 각종 오락기, 노래 반주지 등 정보 기기 등에서 사용하는 실장 제어용 마이크로 프로세서 시장은 매년 10% 이상씩 성장하고 있으며, 21세기 산업을 주도하는 핵심 기술로 자리 매김하고 있다. 이러한 실장 제어용 기기는 마이크로 프로세서와 메모리 및 입출력 자이가 하나의 반도체에 집적되는 경우가 많다. 그런데 반도체 가격은 반도체 크기에 따라 결정되며, 가장 넓은 면적을 차지하는 것은 메모리이다. 따라서 반도체 가격을 낮추기 위해서는 메모리 크기를 줄여야 하며, 이를 위해서 또한 코드 밀도가 높은 컴퓨터 구조에 대한 연구가 필요하다. 최근에는 322비트 RISC 명령어를 16비트 명령어로 축약한 구조가 연구되었다. ARM-7TDMI는 ARM-7의 16비트 축약 명령어 구조이며, TR4101은 MIPS-R3000의 16비트 축약 명령어 구조이다. 이들 16비트 축약 명령어 RISC는 종래 RISC와의 호환성을 위하여 2가지 모드로 동작하므로 구조가 복잡하고, 16비트 명령어에서는 8개의 레지스타만을 접근할 수 있으므로 성능이 크게 떨어지는 단점을 가진다.