• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.325-326
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• 2007

본 논문에서는 H.264 동영상 표준 부호화 방식의 움직임 추정을 위한 고속 다중 참조 프레임 선택 기법에 대해 제안한다. 다중 참조 프레임에 대한 움직임 추정 수행 시 참조 프레임 수에 비례하여 계산량이 증가하는 반면에 동영상의 특성에 따라 부호화 효율의 이득없이 계산량만을 소비하는 경우가 발생된다. 따라서 본 논문에서는 각 참조 프레임에서의 움직임 추정에 대한 SAD값의 비교를 통해 다중 참조 프레임 움직임 추정의 종료 시점을 적응적으로 결정한다 실험 결과를 통해 5개의 참조프레임 사용을 기준으로 제안된 기법을 사용하였을 때 움직임 추정에 소요되는 시간은 가용한 모든 참조 프레임에 대해 움직임 추정을 수행하는 방식 대비 평균 50%정도 감소하였으며, PSNR 및 발생 비트율 측면에서 거의 동일한 성능을 유지함을 확인할 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.3C
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• pp.247-254
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• 2008

H.264 provides a good coding efficiency compared with existing video coding standards, H.263, MPEG-4, based on the use of multiple reference frame for variable block size motion estimation, quarter-pixel motion estimation and compensation, $4{\times}4$ integer DCT, rate-distortion optimization, and etc. However, many modules used to increase its performance also require H.264 to have increased complexity so that fast algorithms are to be implemented as practical approach. In this paper, among many approaches, fast mode decision algorithm by skipping variable block size motion estimation and spatial-predictive coding, which occupies most encoder complexity, is proposed. This approach takes advantages of temporal and spatial properties of fast mode selection techniques. Experimental results demonstrate that the proposed approach can save encoding time up to 65% compared with the H.264 standard while maintaining the visual perspectives.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.53-60
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• 2009

Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.