• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.499-502
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• 1999

This paper presents a PCI (Peripheral Component Interconnect) controller embedded in a multimedia processor, called FLOVA (FLOating point VLIW Architecture), targeting for 3D graphics applications. Fast I/O interfaces are essential for multimedia processors which usually handle large amount of multimedia data. Therefore, in FLOVA, PCI bus is adopted for I/O interface due to fast burst transaction. However, there are several problems in implementation and verification to use burst transaction of PCI. It is difficult to handle data transaction between two units which have two different operating frequency. FLOVA has more higher operating frequency about 100MHz than that of PCI local bus and it makes lower utilization of FLOVA bus. Also, traditional simulation is not sufficient for verification of PCI functionality. In this paper, we propose buffering schemes to implement the PCI controller with wide bandwidth and high bus utilization. Also, this paper shows how to verify the PCI controller using real PCI bus environments before its fabrication.

• Journal of Korea Multimedia Society
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• v.7 no.2
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• pp.251-263
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• 2004

The Synchronized Multimedia Integration Language (SMIL), recommended by the World Wide Web Consortium (W3C) in 1998, is an XML-based declarative language to synchronize and present multimedia documents. SMIL can create new multimedia data integrating various types of multimedia objects which exist separately such as text, video, graphics and audio. It can support synchronization of multimedia data which are limited in current HTML-based Web technology. For its popularity, it is required to develop a multimedia server guaranteeing Quality of Service (QoS), authoring tool and player. For developing a SMIL authoring tool and player, the technologies are essentially required to read and analyze a SMIL document and to play synchronized various types of media objects in a timeline. In this paper, we describe a design and implementation of an event processor which supports SMIL 2.0 timing model. Moreover, we also develop a SMIL 2.0 player using the proposed event processor. This will facilitate the play of SMIL contents, so that it can contribute to the prosperity of SMIL technology It is possible to reuse in various language profiles defined in the SMIL standard. This player is expected to be utilized in other standard integrating SMIL such as XHTML＋SMIL and SMIL Animation.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.1
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• pp.9-18
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• 2004

This paper presents an efficient image compression method for memory reduction in multimedia processor which can be simply implemented in hardware and provides high performance. The multimedia processor, which includes processing of high-resolution images and videos, requires large memories: they are external frame memories to store frames and internal line memories for implementing some linear filters. If we can reduce those memories by adopting a simple compression method in multimedia processor, it will strengthen its cost competitiveness. There exist many standards for efficiently compressing images and videos. However, those standards are too complex for our purpose and most of them are 2-D block-based methods, which do not support raster scanned input and output. In this paper, we propose a low-complexity compression method which has good performance, can be implemented with simple hardware logic, and supports raster scan. We have adopted 1${\times}$8 Hadamard transform for simple implementation in hardware and compression efficiency. After analyzing the coefficients, we applied an adaptive thresholding and quantization. We provide some simulation results to analyze its performance and compare with the existing methods. We also provide its hardware implementation results and discuss about cost reduction effects when applied in implementing a multimedia processor.

• Journal of the Korea Society of Computer and Information
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• v.16 no.1
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• pp.1-9
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• 2011

Recently, as mobile multimedia devices are used more and more, the needs for high-performance and low-energy multimedia processors are increasing. Application-specific integrated circuits (ASIC) can meet the needed high performance for mobile multimedia, but they provide limited, if any, generality needed for various application requirements. DSP based systems can used for various types of applications due to their generality, but they require higher cost and energy consumption as well as less performance than ASICs. To solve this problem, this paper proposes a single instruction multiple data (SIMD) based many-core processor which supports high-performance and low-power image data processing while keeping generality. The proposed SIMD based many-core processor composed of 16 processing elements (PEs) exploits large data parallelism inherent in image data processing. Experimental results indicate that the proposed SIMD-based many-core processor higher performance (22 times better), energy efficiency (7 times better), and area efficiency (3 times better) than conversional commercial high-performance processors.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.11-21
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• 2011

This paper introduces an SIMD(Single Instruction Multiple Data) based parallel processor that efficiently processes massive data inherent in multimedia. In addition, this paper implements MMX(MultiMedia eXtension)-type instructions on the data parallel processor and evaluates and analyzes the performance of the MMX-type instructions. The reference data parallel processor consists of 16 processors each of which has a 32-bit datapath. Experimental results for a JPEG compression application with a 1280x1024 pixel image indicate that MMX-type instructions achieves a 50% performance improvement over the baseline instructions on the same data parallel architecture. In addition, MMX-type instructions achieves 100% and 51% improvements over the baseline instructions in energy efficiency and area efficiency, respectively. These results demonstrate that multimedia specific instructions including MMX-type have potentials for widely used many-core GPU(Graphics Processing Unit) and any types of parallel processors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.117-126
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• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1B
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• pp.17-21
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• 2007

In this paper, we propose new on-line processor management algorithms that manage heterogeneous multimedia services while maximizing energy efficiency. These online management mechanisms are combined in an integrated scheme for higher system performance and energy efficiency. The most important feature of our proposed scheme is its adaptability, flexibility and responsiveness to current network conditions. Simulation results clearly indicate the superior performance of our proposed scheme to strike the appropriate performance balance between contradictory requirements.

• Journal of Broadcast Engineering
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• v.8 no.3
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• pp.259-267
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• 2003

In this paper, we propose a media processor to provide interactive services in mobile multimedia broadcasting environments. The proposed system Is designed to support various functionalities, such as generation of MPEG-4 IOD (Initial Object Descriptor)/OD(Object Descriptor)/BIFS (Binary Format for Scene) data, encapsulation of MPEG-4 AVC (Advanced Video Coding)/BSAC (Bit Sliced Arithmetic Coding) stream and generated IOD/OD/BIFS data into SL (Sync Layer) packet, packetization of SL packet into TS (Transport Stream) packet and multiplexing. The proposed media processor can provide MPEG-4 based interactive services for users.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.23-32
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• 2007

This paper proposes a reconfigurable parallel processor architecture which can efficiently implement various multimedia applications, such as 3D graphics, H.264/H.263/MPEG-4, JPEG/JPEG2000, and MP3. The proposed architecture directly connects memories and processors so that memory access time and power consumption are reduced. It supports floating-point operations needed in the geometry stage of 3D graphics. It adopts partitioned SIMD to reduce hardware costs. Conditional execution of instructions is used for easy development of parallel algorithms.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.503-506
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• 1998

본 논문은Multimedia video processor로써 멀티미디어 데이터, 특히 비디오데이타 처리에 적합?록 구성되어 있는 프로세서이다. TMS320C80에 Multimedia OS를 사용할 경우에 효율성의 타당성을 검증하기 위하여 영상처리를 3가지 방법으로 수행시켜 그 결과를 비교한다. 채택한 영상처리로 DCT와 2차 Laplacian을 채택하였고 이를 적용하는 방법은 첫째, 일반적인 순차적으로 수행하는 방법과 둘째 기본으로 제공되는 kernel의 규약을 따르는 방법, 셋째로 OS모델을 따르는 경우의 방법으로 연산한다. 이 결과 첫번째 두번째 세번째 경우의 순서로 효율이 높은 결과를 얻었다. 이는 구현 방법이 복잡한 응용에 사용되어질 경우, OS모델이 우수할 것임을 반증한다. 이와 같은 결과를 토대로 TMS320C80에 적합한 task managing 부분의 OS kernel model을 제시한다.