• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.202-202
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• 2008

The world gross market of many kinds of electronics, such as TV and mobile phone has been increasing rapidly these days. It is mainly caused by the amazing developments of IT technology during past decade and the changes of individual life style for the better. Thanks to the increases of electronics manufactured in quantity, much more electronic components such as MLCC (multi layer ceramic capacitor) and PCB (printed circuit board), which are our main products, have been needed as a consequence. Though it was reported that total market of electronic components exceeds several hundreds of billion dollars, there are many manufactures struggling for survival in the competition of electronics components. Then the recognition of quality as a key technology has spread and the efforts for high-yield production lines have been kept in many companies. In this paper, our efforts to eliminate the contamination of particles and the diffusion of some volatile organic compounds which is very harmful to workers at production line have been introduced.

• Proceedings of the KWS Conference
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• 2005.11a
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• pp.225-227
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• 2005

Sn-8wt%Zn-3wt%Bi (이하, Sn-8Zn-3Bi) 솔더의 장기 신뢰성을 평가하기 위하여 열 충격 시험을 행하였다. 열 충격 시험은 $-40^{\circ}C$에서 $80^{\circ}C$범위에서 1000 사이클 동안 하였다. 접합 기판으로는 각각 OSP(Organic Solderability Preservative), Sn 그리고 Ni/Au 처리를 한 PCB(Printed Circuit Board) 패드를 사용하였다. 접합에 사용한 부품은 1608 Chip(Multi Layer Chip Capacitor, Chip Resistor) 으로 전극 부위에 Sn-37wt%Pb, Sn 도금하여 사용하였다. 솔더링 후 1608 Chip의 전단 강도와 솔더링부에서 미세조직 및 IMC(Inter Metallic Compound) 변화를 관찰하였다. 측정결과, Sn-8Zn-3Bi 솔더의 초기 전단 강도는 기판의 표면처리에 상관없이 약 40N 이상이었다. 그리고 열충격 시험 1000 사이클 후에는 모든 기판에서 2N 정도 약간의 강도 저하를 보였다.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.15-22
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• 2013

Low-Temperature-cofired ceramics (LTCC) antenna packages have been extensively researched and utilized in recent years due to its excellent electrical properties and ease of implementing dense package integration topologies. This paper introduces some of the key research and development activities using LTCC packaging solutions for 60 GHz antennas at Samsung Electronics [1]. The LTCC 60 GHz antenna element topology is presented and its measured results are illustrated. However, despite its excellent performance, the high cost issues incurred with LTCC at millimeter wave (mmWave) frequencies for antenna packages remains one of the key impediments to mass market commercialization of mmWave antennas. To address this matter, for the first time to the author's best knowledge this paper alleviates the high cost of mmWave antenna packaging by devising a novel, broadband antenna package that is wholly based on low-cost, high volume FR4 Printed Circuit Board (PCB). The electrical properties of the FR4 substrate are first characterized to examine its feasibility at 60 GHz. Afterwards a compact multi-layer antenna package which exhibits more than 9 GHz measured bandwidth ($S_{11}{\leq}-10$ dB) from 57~66 GHz is devised. The measured normalized far-field radiation patterns and radiation efficiency are also presented and discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Proceedings of the KWS Conference
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• 2005.11a
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• pp.228-230
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• 2005

Sn-8wt%Zn-3wt%Bi (이하, Sn-8Zn-3Bi) 솔더의 장기 신뢰성을 평가하기 위하여 고용고습시험을 행하였다. 고온 고습 시험은 $85^{\circ}C$/85RH 조건에서 1000 시간 동안 하였다. 접합 기판으로는 각각 OSP (Organic Solderability Preservative), Sn 그리고 Ni/Au 처리를 한 PCB(Printed Circuit Board) 패드를 사용하였다. 접합에 사용한 부품은 1608Chip 으로 MLCC(Multi Layer Ceramic Capacitor 이하, 1608C) 와 Chip Resister(이하, 1608R)을 사용하였으며, 이 두 부품의 전극부위에 Sn-10wt%Pb(이하 Sn-l0PB), Sn을 각각 도금하였다. 솔더링 후 1608C 와 1608R의 전단 접합 강도와 솔더링부에서 Zn상의 변화를 관찰하였다. 측정결과, Sn-8Zn-3Bi 솔더의 초기 전단 접합 강도는 기판의 표면처리에 상관없이 약 40N 이었다. 그러나 고온 고습 시험 1000 시간 후에는 기판의 표면처리에 상관없이 약 30N 까지 감소하였다. 하지만 이는 reference인 Sn-37Pb 솔더의 강도값과 거의 유사하며, 이는 Sn-8Bi-3Zn 솔더의 고온 고습 시험 후 전단강도 특성은 기존 유연솔더와 비교하여 동등이상이라고 평가할 수 있다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.209-209
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• 2007

Passive Device는 RF Circuit을 제작할 때 많은 면적을 차지하고 있으며 이를 감소시키기 위해 여러 연구가 진행되고 있다. 최근 SoP-L 공정을 이용한 많은 연구가 진행되고 있는데 PCB 제작에 이용되는 일반적인 재료와 공정을 그대로 이용함으로써 개발 비용과 시간 면에서 많은 장점을 가지기 때문이다. SoP-L의 또 하나 장점은 다층구조를 만들기가 용이하다는 점이다. 각 층 간에는 Via를 사용하여 연결하게 되는데, RF Circuit은 회로의 구조와 물성에 따라 특성이 결정되며, 그만큼 Via를 썼을 때 그 영향을 생각해야 한다. 본 연구에서는 multi-layer LCP substrate에 다수의 Via를 chain 구조로 형성하여 전기적 특성을 확인하였다. Via가 70um 두께의 substrate를 관통하면서 상층과 하층의 Conductor을 연속적으로 연결하게 된다. 이 구조의 Resistance와 Insertion Loss를 측정하여, Via의 크기 별 수율과 평균적인 Resistance, RF 계측기로 재현성을 확인하였다. 이를 바탕으로 공정에서의 안정성을 확보하고 Via의 크기와 도금방법에 의한 RF Circuit에서의 영향을 파악하여, 앞으로의 RF Device 개발에 도움이 될 것으로 기대한다. 특히 유기물을 이용한 다층구조의 고주파 RF Circuit에 Via를 적용할 때의 영향을 설계에서부터 고려할 수 있는 자료가 될 것이다.

• Korean Journal of Metals and Materials
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• v.47 no.12
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• pp.842-851
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• 2009

The long-term reliability of Sn-0.3wt%Ag-0.7wt%Cu solder joints was evaluated and compared with Sn-3.0wt%Ag-0.5wt%Cu under thermal shock conditions. Test vehicles were prepared to use Sn-0.3Ag-0.7Cu and Sn-3.0Ag-0.5Cu solder alloys. To compare the shear strength of the solder joints, 0603, 1005, 1608, 2012, 3216 and 4232 multi-layer ceramic chip capacitors were used. A reflow soldering process was utilized in the preparation of the test vehicles involving a FR-4 material-based printed circuit board (PCB). To compare the shear strength degradation following the thermal shock cycles, a thermal shock test was conducted up to 2,000 cycles at temperatures ranging from $-40^{\circ}C$ to $85^{\circ}C$, with a dwell time of 30 min at each temperature. The shear strength of the solder joints of the chip capacitors was measured at every 500 cycles in each case. The intermetallic compounds (IMCs) of the solder joint interfaces werealso analyzed by scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDS). The results showed that the reliability of Sn-0.3Ag-0.7Cu solder joints was very close to that of Sn-3.0Ag-0.5Cu. Consequently, it was confirmed that Sn-0.3Ag-0.7Cu solder alloy with a low silver content can be replaced with Sn-3.0Ag-0.5Cu.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.62-62
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• 2008

As micro-system move toward higher speed and miniaturization, requirements for embedding the passive components into printed circuit boards (PCBs) grow consistently. They should be fabricated in smaller size with maintaining and even improving the overall performance. Miniaturization potential steps from the replacement of surface-mount components and the subsequent reduction of the required wiring-board real estate. Among the embedded passive components, capacitors are most widely studied because they are the major components in terms of size and number. Embedding of passive components such as capacitors into polymer-based PCB is becoming an important strategy for electronics miniaturization, device reliability, and manufacturing cost reduction Now days, the dielectric films deposited directly on the polymer substrate are also studied widely. The processing temperature below $200^{\circ}C$ is required for polymer substrates. For a low temperature deposition, bismuth-based pyrochlore materials are known as promising candidate for capacitor $B_2Mg_{2/3}Nb_{4/3}O_7$ ($B_2MN$) multi layers were deposited on Pt/$TiO_2/SiO_2$/Si substrates by radio frequency magnetron sputtering system at room temperature. The physical and structural properties of them are investigated by SEM, AFM, TEM, XPS. The dielectric properties of MIM structured capacitors were evaluated by impedance analyzer (Agilent HP4194A). The leakage current characteristics of MIM structured capacitor were measured by semiconductor parameter analysis (Agilent HP4145B). 200 nm-thick $B_2MN$ muti layer were deposited at room temperature had capacitance density about $1{\mu}F/cm^2$ at 100kHz, dissipation factor of < 1% and dielectric constant of > 100 at 100kHz.