• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.132-139
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• 1993

This paper presents a new performance-driven multi-levelizer which transforms a two-level description into a boolean network of the multilevel structure satisfied with user's costraints, such as chip area, the number of wires and literals, maximum delay, function level, fanin, fanout, etc.. The performance of circuits is estimated by reference to the informations in cell library through the cell mapping phase, and multi-levelization of circuits is constructed by the decomposition using the kernel and factoring concepts. Here, the saving cost of a common subexpression is defined to the sum of area and delay saved, when it is substituted. The experiments with MCNC benchmarks show the efficiency of the proposed method.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.2
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• pp.55-60
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• 2002

This paper presents a controller for the multiple DC motors using the CAN(Controller Area Network). The controller has a benefit of reducing the cable connections and making the controller boards compact through the network including expansibility. CAN, among the field buses, is a serial communication methodology which has the physical layer and the data link layer in the ISO's OSI (Open System Interconnect) 7 layered reference model. It provides the user with many powerful features including multi-master functionality and the ability to broadcast / multicast telegrams. When we use a microprocessor chip embedding the CAN function, the system becomes more economical and reliable to react shortly in the data transmission. The controller, we proposed, is composed of two main controllers and a sub controller, which have built with a one-chip microprocessor having CAN function. The sub controller is plugged into the Pentium PC to perform a CAN communication, and connected to the main controllers via the CAN. Main controllers are responsible for controlling two motors respectively. Totally four motors, actuators for the biped robot in our laboratory, are controlled in the experiment. We show that the four motors are controlled properly to actuate the biped robot through the network in real time.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.334-336
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• 1994

The conventional APF(Active Power Filter) system performs only function which is compensated for source harmonic by injecting harmonic compensation current as well as reactive power component by PWM. This paper presents a new APF which provides the combined functions of VC(Voltage Compensator) and conventional APF, because the structure of APF is similar to stand- alone UPS in parallel type. Single-chip microprocessor plays an important role in controlling each function. Simulation obtained from ACSL are shown to verify multi-functions of new APP.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.2
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• pp.353-368
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• 2023

The four wing unmanned aerial vehicle owns the characteristics of small size, light weight, convenient operation and well stability. But it is easily disturbed by external environmental factors during flight with these disadvantages of short endurance and poor attitude solving ability. For solving these problems, a microprocessor based on STM32 chip is designed and the overall development is completed by the resources such as built-in timer and multi-function mode general-purpose input/output provided by the master micro controller unit, together with radio receiver, attitude meter, barometer, electronic speed control and other devices. The unmanned aerial vehicle can be remotely controlled and send radio waves to its corresponding receiver, control the analog level change of its corresponding channel pins. The master control chip can analyze and process the data to send multiple sets pulse signals of pulse width modulation to each electronic speed control. Then the electronic speed control will transform different pulse signals into different sizes of current value to drive the motor located in each direction of the frame to generate different rotational speed and generate lift force. To control the body of the unmanned aerial vehicle, so as to achieve the operator's requirements for attitude control, the PID controller based on Kalman filter is used to achieve quick response time and control accuracy. Test results show that the design is feasible.

• Journal of Communications and Networks
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• v.11 no.3
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• pp.240-247
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• 2009

The results of performance analysis by adopting the channel scenarios characterized as Weibull fading for an multicarrierdirect sequence-coded division multiple access (MC-DS-CDMA) system are proposed in this investigation. On the other hand, an approximate simple expression with the criterion of bit error rate (BER) versus signal-to-noise ratio (SNR) method is derived for an MC-DS-CDMA system combining with maximal ratio combining (MRC) diversity based on the moment generating function (MGF) formula of Weibull statistics, and it associates with an alternative expression of Gaussian Q-function. Besides, the other point of view on the BER performance evaluation of an MC-DS-CDMA system is not only the assumption of both single-user and multi-user cases applied, but the phenomena of partial band interference (PBI) is also included. Moreover, in order to validate the accuracy in the derived formulas, some of the system parameters, such as Weibull fading parameter (${\beta}$), user number (K), spreading chip number (N), branch number (L), and the PBI (JSR) values, etc., are compared with each other in the numerical results. To the best of author's knowledge, it is a brand new idea which proposes the evaluation of the system performance for an MC-DS-CDMA system over the point of view with Weibull fading channel.

• Journal of Information Processing Systems
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• v.8 no.2
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• pp.347-358
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• 2012

Recently, security researches have been processed on the method to cover a broader range of hacking attacks at the low level in the perspective of hardware. This system security applies not only to individuals' computer systems but also to cloud environments. "Cloud" concerns operations on the web. Therefore it is exposed to a lot of risks and the security of its spaces where data is stored is vulnerable. Accordingly, in order to reduce threat factors to security, the TCG proposed a highly reliable platform based on a semiconductor-chip, the TPM. However, there have been no technologies up to date that enables a real-time visual monitoring of the security status of a PC that is operated based on the TPM. And the TPB has provided the function in a visual method to monitor system status and resources only for the system behavior of a single host. Therefore, this paper will propose a m-TMS (Mobile Trusted Monitoring System) that monitors the trusted state of a computing environment in which a TPM chip-based TPB is mounted and the current status of its system resources in a mobile device environment resulting from the development of network service technology. The m-TMS is provided to users so that system resources of CPU, RAM, and process, which are the monitoring objects in a computer system, may be monitored. Moreover, converting and detouring single entities like a PC or target addresses, which are attack pattern methods that pose a threat to the computer system security, are combined. The branch instruction trace function is monitored using a BiT Profiling tool through which processes attacked or those suspected of being attacked may be traced, thereby enabling users to actively respond.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.325-335
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• 2018

We herein present a study on the active phased array antenna for receiving satellite broadcasting that can electrically align its polarization to that of target transmitters in its moving condition or in the Skew angle arrangement of the broadcasting satellite receiver. Hence, we have developed an active phased array structure composed of the self-developed Vivaldi antenna and multifunction core (MFC) chip, receiving RF front end module, and control units. In particular, the new Vivaldi antenna designed in the Ku-band of 10.7 - 14.5 GHz to receive one desired polarization mode such as the horizontal or vertical by means of an MFC chip and other control units that can control the amplitude and phase of each antenna element. The test results verified that cross-polarization property is 20 dB or higher and the primary beam can be scanned clearly at approximately ${\pm}60^{\circ}$.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.11-19
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• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.48-55
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• 2000

Recently due to rapid improvement of integrated circuit design environment, size of IC design is to become large to possible design System on Chip(SoC) that one chip with multi function enclosed. Also cause to this rapid change, consumption market is require to spend smallest time for new product development. In this paper to propose a methodology can design a large size IC for save time and applied to design of MPEG Layer 2 decoder to can use audio receiver in digital broadcast system. The digital broadcast audio decoder in this paper is pointed to save hardware size as optimizing algorithm. MPEG Layer 2 decoder algorithm is include MAC to can have an effect on hardware size. So coefficients are using sign digit expression. It is for hardware optimization. If using this method can design MAC without multiplier. The designed audio decoder is using 14,000 gates hardware size and save 22% (4000 gates) hardware usage than using multiplier. Also can design MPEG Layer 2 decoder usable digital broadcast receiver for short time.