• Title/Summary/Keyword: Multi Chip

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Fabrication of Hydrophobic/Hydrophilic Pattern as a Template for DNA Chip Microaray (DNA Chip Microarrays를 위한 template로서 소수성 패턴의 제작)

  • Choi, Yong-Sung;Park, Dae-Hee
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.11a
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    • pp.472-475
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    • 2004
  • Microarray-based DNA chips provide an architecture for multi-analyte sensing. In this paper, we report a new approach for DNA chip microarray fabrication. Multifunctional DNA chip microarray was made by immobilizing many kinds of biomaterials on transducers (particles). DNA chip microarray was prepared by randomly distributing a mixture of the particles on a chip pattern containing thousands of m-scale sites. The particles occupied a different sites from site to site. The particles were arranged on the chip pattern by the random fluidic self-assembly (RFSA) method, using a hydrophobic interaction for assembly.

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A GaAs MMIC Multi-Function Chip with a Digital Serial-to-Parallel Converter for an X-band Active Phased Array Radar System (X-대역 능동 위상 배열 레이더 시스템용 디지털 직병렬 변환기를 포함한 GaAs MMIC 다기능 칩)

  • Jeong, Jin-Cheol;Shin, Dong-Hwan;Ju, In-Kwon;Yom, In-Bok
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.6
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    • pp.613-624
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    • 2011
  • An MMIC multi-function chip for an X-band active phased array radar system has been designed and fabricated using a 0.5 ${\mu}m$ GaAs p-HEMT commercial process. A digital serial-to-parallel converter is included in this chip in order to reduce the number of the control interface. The multi-function chip provides several functions: 6-bit phase shifting, 6-bit attenuation, transmit/receive switching, and signal amplification. The fabricated multi-function chip with a relative compact size of 24 $mm^2$(6 mm${\times}$4 mm) exhibits a transmit/receive gain of 24/15 dB and a P1dB of 21 dBm from 8.5 GHz to 10.5 GHz. The RMS errors for the 64 states of the 6-bit phase shift and attenuation were measured to $7^{\circ}$ and 0.3 dB, respectively over the frequency.

A Study on Analysis Chip Waveforms for the DS/CDMA Communication System (DS/CDMA 통신 시스템의 칩 파형 해석 연구)

  • Hong, Hyun-Mun;Kim, Yong-Ro
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.53 no.3
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    • pp.129-133
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    • 2004
  • As In DS/CDMA(direct sequence code division multiple access) system, the system capacity is limited by multiple access interference(MAI), and self-interference(SI) resulting from the multi-path propagation of the desired user signal. This paper, which the approximated analytic chip waveforms are nearly the same as the computer generated chip waveforms are shown. And then, the BER(Bit Error Rate) performances in CDMA system using the approximated analytic chip waveforms are shown.

Highly Integrated DNA Chip Microarrays by Hydrophobic Interaction

  • Park, Yong-Sung;Kim, Do-Kyin;Kwon, Young-Soo
    • KIEE International Transactions on Electrophysics and Applications
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    • v.11C no.2
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    • pp.23-27
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    • 2001
  • Microarray-based DNA chips provide an architecture for multi-analyte sensing. In this paper, we report a new approach for DNA chip microarray fabrication. Multifunctional DNA chip microarrays were made by immobilizing many kinds if DNAs on transducers (particles). DNA chip microarrays were prepared by randomly distributing a mixture of the particles on a chip pattern containing thousands of micro meter-scale sites. The particles occupied different sites from array to array. Each particle cam be distinguished by a tag that is established on the particle. The particles were arranged on the chip pattern by the random fluidic self-assembly (RFSA) method, using hydrophobic interaction.

Performance Analysis of Shared Buffer Router Architecture for Low Power Applications

  • Deivakani, M.;Shanthi, D.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.6
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    • pp.736-744
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    • 2016
  • Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

Processing Control of 0402 Chip used Pb-free Solder in SMT process (무연솔더 적용한 0402 칩의 공정제어)

  • Bang, Jeong-Hwan;Lee, Chang-U;Lee, Jong-Hyeon;Kim, Jeong-Han;Nam, Won-U
    • Proceedings of the KWS Conference
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    • 2007.11a
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    • pp.218-221
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    • 2007
  • The surface mounting technology of 0402 electric chip part is necessary to fabricate a high density and multi-functional module, but there is a limitation of the technology, like as a bridge and self-alignement. This work estimated SMT processing factors of 0402 chip. To obtain optimum SMT process, we evaluated effects of stencil thickness, shape of hole on printability and mountability. Printability shows best results under the thickness of $80{mu}m$ with circle hole shape and 90% square hole shape. In case of chip mounting process, chip mis-alignment and bridge was occurred rarely in same conditions. In more thin stencil thickness, $50{mu}m$, strength of 1005 chip parts was poor, because of amount of printed solder was insufficient.

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