• Title/Summary/Keyword: Multi Antenna GPS

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Implementation and Performance Analysis of Multi-GNSS Signal Collection System using Single USRP

  • Park, Kwi Woo;Choi, Yun Sub;Lee, Min Joon;Lee, Sang Jeong;Park, Chansik
    • Journal of Positioning, Navigation, and Timing
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    • v.5 no.1
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    • pp.11-20
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    • 2016
  • In this paper, a system that can collect GPS L1 C/A, GLONASS G1, and BDS B1I signals with single front-end receiver was implemented using a universal software radio peripheral (USRP) and its performance was verified. To acquire the global navigation satellite system signals, hardware was configured using USRP, antenna, external low-noise amplifier, and external oscillator. In addition, a value of optimum local oscillator frequency was selected to sample signals from three systems with L1-band with a low sampling rate as much as possible. The comparison result of C/N0 between the signal collection system using the proposed method and commercial receiver using double front-end showed that the proposed system had 0.7 ~ 0.8dB higher than that of commercial receiver for GPS L1 C/A signals and 1 ~ 2 dB lower than that of commercial receiver for GLONASS G1 and BDS B1I. Through the above results, it was verified that signals collected using the three systems with a single USRP had no significant error with that of commercial receiver. In the future, it is expected that the proposed system will be combined with software-defined radio (SDR) and advanced to a receiver that has a re-configuration channel.

Design of Low-complexity FFT Processor for Narrow-band Interference Signal Cancellation Based Array Antenna (배열 안테나 기반 협대역 간섭신호 제거를 위한 저면적 FFT 프로세서 설계 연구)

  • Yang, Gi-jung;Won, Hyun-Hee;Park, Sungyeol;Ahn, Byoung-Sun;Kang, Haeng-Ik
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2017.10a
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    • pp.621-622
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    • 2017
  • In this paper, a low-complexity FFT processor is proposed for narrow-band interference signal cancellation based array antenna. The proposed FFT pocessor can support the variable length of 64, 128 and 512. By reducing number of non-tirval multipliers with mixed radix-4/2/4/2/4/2 algorithm and flexible multi-path delay commutator(MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in Xilinx system generator and Implemented with Xilinx Virtex-7 FPGA. With the proposed architecture, the number of slices for the processor is 11454, and the number of DSP48s is 194.

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