• Journal of Institute of Control, Robotics and Systems
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• v.6 no.8
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• pp.697-702
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• 2000

The paper considers the problem of improving the productivity of surface mounting in the printed circuit board(PCB) assembly line. This problem is generally divided into two problems ; real assignment problem and pick-and -place sequencing problem which are known to have no polynomial time algorithms. In the last ten years algorithm designers have been trying to solve them separately. However they need to be solved jointly because they are highly interrelated. This paper proposes an evolutionary algorithm which can consider the two problems jointly and thus yield a better solution. In order to evaluate the proposed algorithm computer simulation is performed on real-life surface mounting machines. The proposed algorithm is expected to reduce the assembly time of surface mounting machines and thus improve the productivity.

• International Journal of Industrial Entomology and Biomaterials
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• v.4 no.1
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• pp.19-22
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• 2002

Rotary mountages are the best mountages among all the mountages that are used in sericultural areas. But to use this mountage more space, separate mounting hall & requires more labour to pickup the matured worms. to over come these problems, self mounting method is adopted to save the time Er labour, But the mounting rate is generally less. To accelerate the mounting rate different repellents viz; saw dust, phytoecdysone, 1% cresol with paddy husk, lime, kaolin, gormalin chaff were used in the present study. The results indicated that highest number of larvae climbed the mountage in 1% cresol with paddy husk, followed by phytoecdysone and lime. It is observed that the use of repellents at wandering stage accilerates mounting rate and did not affect the quality of the cocoons and reeling characters.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.6 no.3
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• pp.24-30
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• 2007

The FPCs(Flexible Printed Circuit) are currently used in several electronic products like digital cameras, cellular phones because of flexible material characteristics. Because the FPC is usually small size and flexible, only one FPC should not enter chip mounting process, instead, several FPCs are placed on the large rigid pallette and enter into the chip mounting process. Currently the job of mounting FPC on the pallette is carried by totally manual way. Thus, the goals of the research is develop the automatic machine of FPC mounting on pallette using vision alignment. Instead of using two cameras or using moving one camera, the proposed vision system with only one fixed camera is adopted. Moreover, the two picker heads which can handle two FPCs simultaneously are used to make process time shortened. The procedure of operation is firstly to measure alignment error of FPC, correct alignment errors, and finally mount well-aligned FPC on the pallette. The vision technology is used to measure alignment error accurately, and precision motion control is used in correcting errors and mounting FPC.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.587-597
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• 2005

Flash memory based embedded computing systems are becoming increasingly prevalent.These systems typically have to provide an instant start-up time. However, we observe that mounting a file system toy flash memory takes 1 to 25 seconds mainly depending on the flash capacity. Since the flash chip capacity is doubled in every year, this mounting time will soon become the most dominant reason of the delay of system start-up time Therefore, in this paper, we present instant mounting techniques for flash file systems by storing the In-memory file system metadata to flash memory when unmounting the file system and reloading the stored metadata quickly when mounting the file system. These metadata snapshot techniques are specifically developed for NOR- and NAND-type flash memories, while at the same time, overcoming their physical constraints. The proposed techniques check the validity of the stored snapshot and use the proposed fast trash recovery techniques when the snapshot is Invalid. Based on the experimental results, the proposed techniques can reduce the flash mounting time by about two orders of magnitude over the existing de facto standard flash file system, JFFS2.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.43 no.4
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• pp.67-75
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• 2020

This paper proposes a methodology for gantry route optimization in order to maximize the productivity of a odd-type surface mount device (SMD). A odd-type SMD is a machine that uses a gantry to mount electronic components on the placement point of a printed circuit board (PCB). The gantry needs a nozzle to move its electronic components. There is a suitability between the nozzle and the electronic component, and the mounting speed varies depending on the suitability. When it is difficult for the nozzle to adsorb electronic components, nozzle exchange is performed, and nozzle exchange takes a certain amount of time. The gantry route optimization problem is divided into the mounting order on PCB and the allocation of nozzles and electronic components to the gantry. Nozzle and electronic component allocation minimized the time incurred by nozzle exchange and nozzle-to-electronic component compatibility by using an mixed integer programming method. Sequence of mounting points on PCB minimizes travel time by using the branch-and-price method. Experimental data was made by randomly picking the location of the mounting point on a PCB of 800mm in width and 800mm in length. The number of mounting points is divided into 25, 50, 75, and 100, and experiments are conducted according to the number of types of electronic components, number of nozzle types, and suitability between nozzles and electronic components, respectively. Because the experimental data are random, the calculation time is not constant, but it is confirmed that the gantry route is found within a reasonable time.

• Journal of the Korea Institute of Military Science and Technology
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• v.12 no.5
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• pp.636-643
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• 2009

NHC means that the velocity of the vehicle in the plane perpendicular to the forward direction is almost zero. The main error source of NHC is the mounting misalignment which is the difference between the body frame of a land vehicle and the sensor frame of an inertial measurement unit. This paper suggests new NHC algorithm that can reduce position errors by real-time estimation of mounting misalignment. Then NHC/ZUPT integrated land navigation system is designed and its performances are analyzed by simulations with van test data. Simulation results show that the proposed NHC/ZUPT land navigation system improves navigation accuracy regardless of misalignment angle and is very useful when SDINS operates stand-alone for land vehicle navigation with large mounting misalignment.

• Journal of Sericultural and Entomological Science
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• v.37 no.2
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• pp.127-131
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• 1995

A crude crystal of phytoecdysone was obtained 355 mg per Kg dry radix of A. japonica, and it was identified to $\beta$-ecdysone by TLC. Feeding silkworms on mulberry leaves sprayed with the extract, mounting time shortened and pupation ratio improved. The feeding effects of the extract was differed according to the rearing seasons, spring and summer. In spring season, only mounting time shortened without any difference in pupation ratio from the control. In summer season, not only mounting time shortened, but also pupation ratio remarkably advanced.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.10a
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• pp.276-280
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• 2001

In the development of Chip Mounter(C/M), much interests have risen regarding how to decrease the operation time of mounting the different chips on the printed circuit board(PCB). The existing method to determine the time sequence of teaching C/M was to follow the procedure which was made by the operater. IN this study, a new but effective algorithm has been developed and employed in SCM-130 Chip Mounter and its online programming had reduced the mounting time significantly and provided the basis for the future online CAD/CAM system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• Journal of Information Technology Applications and Management
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• v.11 no.2
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• pp.29-43
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• 2004

As the development of an information technique, gradually, mobile device is going to be miniaturized and operates at high speed. By such the requirements, the devices using a flash memory as a storage media are increasing. The flash memory consumes low power, is a small size, and has a fast access time like the main memory. But the flash memory must erase for recording and the erase cycle is limited. JFFS is a representative filesystem which reflects the characteristics of the flash memory. JFFS to be consisted of LSF structure, writes new data to the flash memory in sequential, which is not related to a file size. Mounting a filesystem or an error recovery is achieved through the sequential approach. Therefore, the mounting delay time is happened according to the file system size. This paper proposes a MJFFS to use a multi-checkpoint information to manage a mass flash file system efficiently. A MJFFS, which improves JFFS, divides a flash memory into the block for suitable to the block device, and stores file information of a checkpoint structure at fixed interval. Therefore mounting and error recovery processing reduce efficiently a number of filesystem access by collecting a smaller checkpoint information than capacity of actual files. A MJFFS will be suitable to a mobile device owing to accomplish fast mounting and error recovery using advantage of log foundation filesystem and overcoming defect of JFFS.