• Title/Summary/Keyword: Most Significant Bit first multiplication

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Cellular Automata based on VLSI architecture over GF($2^m$) (GF($2^m$)상의 셀룰라 오토마타를 이용한 VLSI 구조)

  • 전준철;김현성;이형목;유기영
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.12 no.3
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    • pp.87-94
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    • 2002
  • This study presents an MSB(Most Significant Bit) Int multiplier using cellular automata, along with a new MSB first multiplication algorithm over GF($2^m$). The proposed architecture has the advantage of high regularity and a reduced latency based on combining the characteristics of a PBCA(Periodic Boundary Cellular Automata) and with the property of irreducible AOP(All One Polynomial). The proposed multiplier can be used in the effectual hardware design of exponentiation architecture for public-key cryptosystem.

A New Arithmetic Unit Over GF(2$^{m}$ ) for Low-Area Elliptic Curve Cryptographic Processor (저 면적 타원곡선 암호프로세서를 위한 GF(2$^{m}$ )상의 새로운 산술 연산기)

  • 김창훈;권순학;홍춘표
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.7A
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    • pp.547-556
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    • 2003
  • This paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for low-area elliptic curve cryptographic processor. The proposed arithmetic unit, which is linear feed back shift register (LFSR) architecture, is designed by using hardware sharing between the binary GCD algorithm and the most significant bit (MSB)-first multiplication scheme, and it can perform both division and multiplication in GF(2$^{m}$ ). In other word, the proposed architecture produce division results at a rate of one per 2m-1 clock cycles in division mode and multiplication results at a rate of one per m clock cycles in multiplication mode. Analysis shows that the computational delay time of the proposed architecture, for division, is less than previously proposed dividers with reduced transistor counts. In addition, since the proposed arithmetic unit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Therefore, the proposed novel architecture can be used for both division and multiplication circuit of elliptic curve cryptographic processor. Specially, it is well suited to low-area applications such as smart cards and hand held devices.

The properties Analysis of IDEA algorithm (IDEA 알고리즘의 특성 분석)

  • 김지홍;장영달;윤석창
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.3A
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    • pp.399-405
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    • 2000
  • In this paper, we deal with block cipher algorithm IDEA(international data encryption algorithm), previously known as typical block cipher system. first of all, analysing key scheduler we classify the key sequences with the used key bit and the unused key bits in each round. with this properties we propose the two method, which are differential analysis using differences of plaintext pairs and linear analysis using LSB bit of plaintexts and key sequences.

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Optimizing Multiprecision Squaring for Efficient Public Key Cryptography on 8-bit Sensor Nodes (8 비트 센서 노드 상에서 효율적인 공개키 암호를 위한 다정도 제곱 연산의 최적화)

  • Kim, Il-Hee;Park, Yong-Su;Lee, Youn-Ho
    • Journal of KIISE:Computer Systems and Theory
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    • v.36 no.6
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    • pp.502-510
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    • 2009
  • Multiprecision squaring is one of the most significant algorithms in the core public key cryptography operation. The aim of this work is to present a new improved squaring algorithm compared with the MIRACL's multi precision squaring algorithm in which the previous work [1] on multiprecision multiplication is implemented. First, previous works on multiprecision multiplication and standard squaring are analyzed. Then, our new Lazy Doubling squaring algorithm is introduced. In MIRACLE library [3], Scott's Carry-Catcher Hybrid multiplication technique [1] is applied to implementation of multiprecision multiplication and squaring. Experimental results of the Carry-Catcher hybrid squaring algorithm and the proposed Lazy Doubling squaring algorithm both of which are tested on Atmega128 CPU show that proposed idea has achieved significant performance improvements. The proposed Lazy Doubling Squaring algorithm reduces addition instructions by the fact $a_0\;{\ast}\;2\;+\;a_1\;{\ast}\;2\;+\;...\;+\;a_{n-1}\;{\ast}\;2\;+\;a_n\;{\ast}\;2\;=\;(a_0\;+\;a_1\;+\;...\;+\;a_{n-1}\;+\;a_n)\;{\ast}\;2$ while the standard squaring algorithm reduces multiplication instructions by the fact $S_{ij}\;=\;x_i\;{\ast}\;x_j\;=\;S_{ij}$. Experimental results show that the proposed squaring method is 25% faster than that in MIRACL.